TC1724 Datasheet, PDF (130/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
Electrical Parameters
• Updated max limit of ΣI_IN.
• Added I_IN.
• Added Pin Reliability in Overload subchapter.
• Removed sentence “Exposure to conditions within the maximum ratings will not
affect device reliability.” Replaced with the Pin Reliability in Overload subchapter.
• Added definition of driver strength settings, updated footnote 4 for ERAY Interface
Timing
• Updated max limits of Flash parameters t_PRD, t_PRP
• Updated representation of I_DDP
• Updated limits of I_{DD_PORST} to max 110mA
• Updated limits of I_{DDP_PORST} to max 6mA
• Updated limits of I_DD for real pattern, f_CPU=133MHz, to max 212mA
• Added new parameter I_DDSUM
• Updated max limit of I_DDM to 32mA
• Updated TC1724 I_V5 for max and real patterns, with and without ERAY, f_CPU=133MHz
• Updated TC1724 I_V5 for max pattern, f_CPU=80MHz
• Updated PD for real pattern, f_{CPU=133MHz, all external supplies.}
• Updated TC1724 PD for max and real patterns, with and without ERAY, f_CPU=133MHz,
5V only with external pass device.
• Updated TC1724 PD for max and real patterns, f_{CPU=80MHz, 5V only without external pass device.}
• Updated limit for R_DSON2 of A2 pad, P_MOS
• Removed V_IH for Pass Device Detector
• Updated limits for V_IL of Pass Device Detector
• Updated limits and test conditions for ∆V_LOREG33 and ∆V_LIREG33
• Updated test condition for 5.0V single supply ∆V_LOREG13
• Updated limits and test condition for 5.0V single supply ∆V_LIREG13
• Corrected typ and max limits for C_OUT33 and C_OUT13
• Added limit and test condition for 3.3V single supply ∆V_LOREG13 and ∆V_LIREG13
• Application reset boot time limits are updated
• Added min limit for I_OZS
• Added a new parameter V_ILSD
• Updated limits for t_BP, STT
• Removed typical text from load of Peripheral Timing sections.
• Limits for EF_GRAD with Gain=4 is changed to TBD
• Min limit for V_DDM is changed to TBD
• Added EF_REFI
• Added a placeholder for R_FAIN, EF_DNL, EF_INL, EF_GRAD, EF_OFF at a separate ADC table
for V_DDM=3.3V
• Added max and typ limits for R_RAIN for V_DDM=3.3V
• Updated limits of P_D for real pattern, f_CPU=80MHz, to max 669mW
• Added new variant SAK-TC1724F-192F80HR
• Updated text for Note column of N_E
Data Sheet
5-85
V1.2, 2014-06