TC1724 Datasheet, PDF (128/134 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1724
Electrical Parameters
– Updated I_DDP, I_DDM, I_{DDP_FP}
– Added I_DD for f_CPU=80MHz for max and realistic patterns
– Updated PD values for max and real patterns, all external, f_CPU=133MHz
– Added text to of f_CPU=133MHz to the note for the PD parameter.
– Added PD for f_CPU=80Mhz for max and realistic patterns for both all external mode
and 5V only with ext.pass device mode
– Current consumption for LVDS pad pairs is updated for all LVDS pads in total
– Deleted the redundant I_DDP
– Updated I_{DDP_FP,} I_{DDP_PORST}, I_{DD_PORST}
– Deleted R_THJA parameter
• Power Sequencing
– Added Power Sequencing for 3.3V Supply Only section
• Power, Pad and Reset Timing parameters
– Removed redundant note for t_HDH, t_HDS
– Added text from note “TESTMODE/TRST” to the name of t_POH and t_POS, deleted
note
• EVR Parameters
– Added I_{PU_VDPG}, V_IH and V_IL parameters in Pass Device Detector Table
– Added EVR Parameter Table
• PLL SYSCLK parameters
– Changed max value for f_VCO
– Added min value of 50us for t_L
– Included formula 1 and 2
– Removed note for peak-to-peak noise on pad supply voltage
• PLL ERAY parameters
– Changed typ value to 250MHz for f_PLLBASE
– Added min value of 50us for t_L
– Removed note for peak-to-peak noise on pad supply voltage
• JTAG Interface parameters
– Changed to ‘=’ signs in the notes for t₈, t₉ and t₁₀
• DAP parameters
• Peripheral Timings
– Removed note for Peripheral Timings “Peripheral timing parameters are not
subject to production test. They are verified by design/characterization.”
• MLI Timing
– Added text for MLI parameters valid for CL=25pF
• MLI Receiver parameters
– Changed f_SYS to 110MHz in footnote 3
• MLI Tranmitter parameters
– Changed t₁₃, TCLK rise time and t₁₄, TCLK fall time to 0.3 x t10
• MSC parameters
– Added text for MSC parameters valid for CL=25pF
– Added limits for different pad drive strength of t₄₅
Data Sheet
5-83
V1.2, 2014-06