HYB25L256160AF Datasheet, PDF (36/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Timing Diagrams
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High Level
is required
CS
RAS
CAS
WE
BS
AP
Addr.
DQM
t _RP
Hi-Z
DQ
Minimum of 8 Refresh Cycles are required
2 Clock min.
Address Key
t _RC
Precharge
Command
All Banks
Inputs must be 1st Auto Refresh
stable for 200 µs Command
8th Auto Refresh
Command
Figure 19 Power on Sequence and Auto Refresh (CBR)
Mode Register Any
Set Command Command
SPT03913
Data Sheet
36
Rev. 1.2, 04-2004