HYB25L256160AF Datasheet, PDF (14/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Functional Description
3.2.2 Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Table 4.
Table 4
Burst
Length
2
4
8
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Note:
1. For a burst length of two, Ai-A1 selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, Ai-A2 selects the four-data-element block; A1-A0 selects the first access within the
block.
3. For a burst length of eight, Ai-A3 selects the eight-data- element block; A2-A0 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3 Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2 and 3 clocks.
If a Read command is registered at rising clock edge n, and the latency is m clocks, the data is available nominally
coincident with rising clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
3.2.4 Operating Mode
The normal operating mode is selected by issuing a Mode Register Set Command with bits A12-A7 set to zero,
and bits A6-A0 set to the desired values. Burst Length for Write bursts is fixed to one by issuing a Mode Register
Set command with bits A12-A10 and A8-A7 each set to zero, bit A9 set to one, and bits A0-A6 set to the desired
values.
All other combinations of values for A12-A7 are reserved for future use and/or test modes. Test modes and
reserved states should not be used as unknown operation or incompatibility with future versions may result.
Data Sheet
14
Rev. 1.2, 04-2004