HYB25L256160AF Datasheet, PDF (27/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Timing Diagrams
(CAS latency = 3)
T0
T1
T
T
CLK
Address
Bank B
Row Addr.
Command
Bank B
Activate
t _RCD
NOP NOP
"H" or "L"
Bank B
Col. Addr.
Write B
with Auto
Precharge
t _RC
Figure 5 Bank Activate Command Cycle
T
T
T
Bank A
Row Addr.
Bank A
Activate
t _RRD
NOP
Bank B
Row Addr.
Bank B
Activate
SPT03784
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command Read A NOP NOP NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Figure 6 Burst Read Operation
SPT03712
Data Sheet
27
Rev. 1.2, 04-2004