HYB25L256160AF Datasheet, PDF (16/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Functional Description
3.4
Commands
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive
edge of the clock. The following list shows the truth table for the operation commands.
Table 5 Operation Definition¹⁾
Operation
Bank Active
Device
State
Idle³⁾
CKE CKE DQM BA1 AP= Addr CS RAS CAS WE
n-1²⁾ n²⁾
BA0 A10
H X X V V V LL H H
Bank Precharge
Any
H X X V L X LL H L
Precharge All
Write
Write with Autoprecharge
Read
Read with Autoprecharge
Any
Active³⁾
Active³⁾
Active³⁾
Active³⁾
HXX
HXX
HXX
HXX
HXX
XHX
VL V
VHV
VL V
VHV
LL H L
LH L L
LH L L
LH L H
LH L H
Mode Register Set
Idle
H X X V V V LL L L
No Operation
Any
H X X X X X LH H H
Burst Stop
Active
H X X X X X LH H L
Device Deselect
Any
H X X X X X HX X X
Auto Refresh
Idle
H H X X X X LL L H
Self Refresh Entry
Idle
H L X X X X LL L H
Self Refresh Exit
Idle
(Self Refresh)
HX X X
L H X X X X _{LH H X}
Clock Suspend Entry
Active⁴⁾
H L X X X X XX X X
Clock Suspend Exit
Active
L H X X X X XX X X
Power Down Entry
Idle
(Precharge or active standby) _Active4)
HX X X
H L X X X X _{LH H H}
Power Down Exit
Any
(Power Down)
HX X X
L H X X X X _{LH H L}
Data Write/Output Enable Active
H X L X X X XX X X
Data Write/Output Disable Active
H X H X X X XX X X
Deep Power Down Entry
Idle
H L X X X X LH H L
Deep Power Down Exit
Deep Power Down⁵⁾ L H X X X X X X X X
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level.
2) CKE_n signal is input level when commands are provided, CKE_n-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst
cycle the device enters Clock Suspend Mode.
5) After Deep Power Down mode exit a full new initialisation of the memory device is mandatory.
Data Sheet
16
Rev. 1.2, 04-2004