HYB25L256160AF Datasheet, PDF (31/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

Write and Read Interrupt
HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Write B NOP NOP NOP NOP NOP NOP
1 Clk Interval
DQ’s
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
Figure 12 Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Read B NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t _CK2, DQ’s
CAS
latency = 3
t _CK3, DQ’s
DIN A0 don’t care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0 don’t care don’t care
Input data for the Write is ignored.
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQ’s
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
SPT03719
Figure 13 Write Interrupted by a Read
Data Sheet
31
Rev. 1.2, 04-2004