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HYB25L256160AF Datasheet, PDF (28/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM
HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command Read A Read B NOP NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t CK2, DQ’s
CAS
latency = 3
t CK3, DQ’s
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3
SPT03713
Figure 7 Read Interrupted by a Read
Read to Write Interval
(Burst Length = 4, CAS latency = 3)
T0
T1
T2
T3
T4
T5
CLK
Minimum delay between the Read and Write
Commands = 4 + 1 = 5 cycles
DQMx
t DQZ
Command NOP Read A NOP NOP NOP NOP
T6
T7
T8
Write latency t DQW of DQMx
Write B NOP NOP
DQ’s
"H" or "L"
Figure 8 Read to Write Interval
DOUT A0
DIN B0
Must be Hi-Z before
the Write Command
DIN B1
DIN B2
SPT03787
Data Sheet
28
Rev. 1.2, 04-2004