HYB25L256160AF Datasheet, PDF (11/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Pin Configuration
Column Address
Counter
Column Addresses
A0 - A8, AP,
BA0, BA1
Column Address
Buffer
Row Addresses
A0 - A12,
BA0, BA1
Row Address
Buffer
Refresh Counter
Row
Decoder
Memory
Array
Bank 0
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 1
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 2
8192 x 512
x 16 Bit
Row
Decoder
Memory
Array
Bank 3
8192 x 512
x 16 Bit
Input Buffer Output Buffer
DQ0 - DQ15
Control Logic &
Timing Generator
SPB04124_256M
Figure 2 Block Diagram (16 Mbit × 16, 13 / 9 / 2 Addressing)
Note:
1. This Functional Block Diagram is intended to facilitate user understanding of the operation of the device; it does
not represent an actual circuit implementation.
2. DQM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional
DQ signals.
Data Sheet
11
Rev. 1.2, 04-2004