HYB25L256160AF Datasheet, PDF (30/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM

HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Timing Diagrams
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
t _DQW
t _DQZ
Command NOP Read A NOP NOP Read A NOP Write B NOP NOP
CAS
latency = 2
t _CK2, DQ’s
Must be Hi-Z before
the Write Command
DOUT A0 DOUT A1
DIN B0
DIN B1
DIN B2
CAS
latency = 3
t _CK3, DQ’s
DOUT A0
DIN B0 DIN B1 DIN B2
"H" or "L"
SPT03940
Figure 10 Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A NOP NOP NOP NOP NOP NOP NOP
DQ’s
DIN A0 DIN A1 DIN A2 DIN A3 don’t care
The first data element and the Write
are registered on the same clock edge.
Figure 11 Burst Write Operation
Extra data is ignored after
termination of a Burst.
SPT03790
Data Sheet
30
Rev. 1.2, 04-2004