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HYB25L256160AF Datasheet, PDF (22/56 Pages) Infineon Technologies AG – 256MBit Mobile-RAM
HY[B/E]25L256160AF–7.5
256MBit Mobile-RAM
Electrical Characteristics
Table 9 Input and Output Capacitances
Parameter
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ
Symbol
CI1
CI2
CIO
Values
min. typ. max.
–
– 3.5
–
– 3.8
4.0 – 5.0
Unit
pF
pF
pF
Note/
Test Condition
1)
1)
1)
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f = 1 MHz,
TCASE = 25 °C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
4.2
Timing Characteristics
Table 10 AC Timing Characteristics1)2)
Parameter
Clock
DQ output access time from CLK
CK high-level width
CK low-level width
Clock cycle time
Clock frequency
Setup and Hold Times
Input setup time
Input hold time
CKE setup time
CKE hold time
Mode register setup time
Power down moder entry time
Common Parameters
Active to Read or Write delay
Precharge command period
Active to Precharge command
Active bank A to Active bank A period
Active bank A to Active bank B delay
CAS to CAS command delay
Symbol
tAC3
tAC2
tCH
tCL
tCK3
tCK2
fCK3
fCK2
tIS
tIH
tCKS
tCKH
tRSC
tSB
tRCD
tRP
tRAS
tRC
tRRD
tCCD
–7.5
min. max.
Unit Note/ Test Condition
–
7.5
–
6
–
5.4
–
7.5
–
6
2.5 –
2.5 –
7.5 –
8
–
9.5 –
–
133
–
125
–
105
ns VDDQ < 2.3 V 3)4)5)8)
ns VDDQ ≥ 2.3 V 3)4)5)8)
ns VDDQ ≥ 3.0 V 3)4)5)8)
ns VDDQ < 2.3 V 3)4)5)8)
ns VDDQ ≥ 2.3 V 3)4)5)8)
ns –
ns –
ns VDDQ ≥ 2.3 V 3)
ns VDDQ < 2.3 V 3)
ns 3)
MHz
MHz
MHz
VDDQ ≥ 2.3 V 3)
VDDQ < 2.3 V 3)
3)
1.5 –
0.8 –
1.5 –
0.8 –
2
–
0
7.5
ns 6)
ns 6)
ns 6)
ns 6)
tCK –
ns –
19
–
ns 7)
19
–
ns 7)
45
100000 ns 7)
67
–
ns 7)
15
–
ns 7)
1
–
tCK –
Data Sheet
22
Rev. 1.2, 04-2004