TLE9260-3QX Datasheet, PDF (153/175 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9260-3QX
Serial Peripheral Interface
DEV_STAT
Device Information Status (Address 100 0011_B)
POR / Soft Reset Value: 0000 0000_B; Restart Value: xx00 xxxx_B
7
6
5
4
3
2
1
DEV_STAT_1 DEV_STAT_0 Reserved
rc
rc
r
Reserved WD_FAIL_1 WD_FAIL_0 SPI_FAIL
r
r
rh
rh
rc
0
FAILURE
rc
Field
Bits
DEV_STAT 7:6
Reserved 5:4
WD_FAIL 3:2
SPI_FAIL 1
FAILURE 0
Type
rc
r
rh
rc
rc
Description
Device Status before Restart Mode
00_B , Cleared (Register must be actively cleared)
01_B , Restart due to failure (WD fail, TSD2, VCC1_UV); also after a
wake from Fail-Safe Mode
10_B , Sleep Mode
11_B , Reserved
Reserved, always reads as 0
Number of WD-Failure Events (1/2 WD failures depending on
CFG)
00_B , No WD Fail
01_B , 1x WD Fail, FOx activation - Config 2 selected
10_B , 2x WD Fail, FOx activation - Config 1 / 3 / 4 selected
11_B , Reserved (never reached)
SPI Fail Information
0_B , No SPI fail
1_B , Invalid SPI command detected
Activation of Fail Output FO
0_B , No Failure
1_B , Failure occurred
Notes
1. The bits DEV_STAT show the status of the device before it went through Restart. Either the device came from
regular Sleep Mode (‘10’) or a failure (‘01’ - SBC Restart or SBC Fail-Safe Mode: WD fail, TSD2 fail, VCC_UV
fail or VCC1_OV if bit VCC1_OV_RST is set) occurred. Failure is also an illegal command from SBC Stop to
SBC Sleep Mode or going to SBC Sleep Mode without activation of any wake source. Coming from SBC Sleep
Mode (‘10’) will also be shown if there was a trial to enter SBC Sleep Mode without having cleared all wake
flags before.
2. The WD_FAIL bits are configured as a counter and are the only status bits, which are cleared automatically
by the SBC. They are cleared after a successful watchdog trigger and when the watchdog is stopped (also in
SBC Sleep and Fail-Safe Mode unless it was reached due to a watchdog failure). See also Chapter 12.1.
3. The SPI_FAIL bit is cleared only by SPI command
4. In case of Config 2/4 the WD_Fail counter is frozen in case of WD trigger failure until a successful WD trigger.
5. If CFG = ‘0’ then a 1st watchdog failure will not trigger the FO outputs or the FAILURE bit but only force the
SBC into SBC Restart Mode.
Data Sheet
153
Rev. 1.1, 2014-09-26