TLE9260-3QX Datasheet, PDF (148/175 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

TLE9260-3QX
Serial Peripheral Interface
Table 31 Recommended CDR Settings for Different Baud Rates
SEL_OSC_CLK Baudrate SWK_BTL1_CTRL
[1:0]
Value
SWK_CDR_LIMIT_HIGH SWK_CDR_LIMIT_LOW
_CTRL Value
_CTRL Value
00
500k
1010 0000
1010 1000
1001 1000
01
500k
0101 0000
0101 0100
0100 1100
10
500k
CDR Setting not recommended for this baudrate due to insufficient precision
11
500k
CDR Setting not recommended for this baudrate due to insufficient precision
00
250k
CDR Setting not to be used due to excessive time quanta (counter overflow)
01
250k
1010 0000
1010 1000
1001 1000
10
250k
0101 0000
0101 0100
0100 1100
11
250k
CDR Setting not recommended for this baudrate due to insufficient precision
00
125k
CDR Setting not to be used due to excessive time quanta (counter overflow)
01
125k
CDR Setting not to be used due to excessive time quanta (counter overflow)
10
125k
1010 0000
1010 1000
1001 1000
11
125k
0101 0000
0101 0100
0100 1100
SWK_CDR_LIMIT_HIGH_CTRL
SWK CDR Upper Limit Control (Address 011 1110_B)
POR / Soft Reset Value: 1010 1000_B; Restart Value: xxxx xxxx_B
7
6
5
4
3
CDR_LIM_
H_7
rw
CDR_LIM_
H_6
rw
CDR_LIM_
H_5
rw
CDR_LIM_
H_4
rw
CDR_LIM_
H_3
rw
2
1
CDR_LIM_ CDR_LIM_
H_2
H_1
r
rw
rw
0
CDR_LIM_
H_0
rw
Field
Bits
CDR_LIM_H 7:0
Type
rw
Description
Upper Bit Time Detection Range of Clock and Data Recovery
SWK_BTL1_CTRL values > + 5% will be clamped
SWK_CDR_LIMIT_LOW_CTRL
SWK CDR Lower Limit Control (Address 011 1111_B)
POR / Soft Reset Value: 1001 1000_B; Restart Value: xxxx xxxx_B
7
6
5
4
3
CDR_LIM_
L_7
rw
CDR_LIM_
L_6
rw
CDR_LIM_
L_5
rw
CDR_LIM_
L_4
rw
CDR_LIM_
L_3
rw
2
1
CDR_LIM_ CDR_LIM_
L_2
L_1
r
rw
rw
0
CDR_LIM_
L_0
rw
Field
Bits
CDR_LIM_L 7:0
Type
rw
Description
Lower Bit Time Detection Range of Clock and Data Recovery
SWK_BTL1_CTRL values < - 5% will be clamped
Data Sheet
148
Rev. 1.1, 2014-09-26