TLE9260-3QX Datasheet, PDF(117/175 Page) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

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TLE9260-3QX Datasheet, PDF (117/175 Pages) Infineon Technologies AG – Dedicated Data Sheets are available for the different product variants

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TLE9260-3QX

Serial Peripheral Interface

M_S_CTRL

HW_CTRL

WD_CTRL

BUS_CTRL_1

BUS_CTRL_2

WK_CTRL_1

WK_CTRL_2

WK_PUPD_CTRL

WK_FLT_CTRL

TIMER1_CTRL

TIMER2_CTRL

SW_SD_CTRL

HS_CTRL_1

HS_CTRL_2

GPIO_CTRL

PWM1_CTRL

PWM2_CTRL

PWM_FREQ_CTRL

SYS_STAT_CTRL

SWK_CTRL

SWK_BTL1_CTRL

SWK_BTL2_CTRL

SWK_ID3_CTRL

SWK_ID2_CTRL

SWK_ID1_CTRL

SWK_ID0_CTRL

SWK_MASK_ID3_CTRL

SWK_MASK_ID2_CTRL

SWK_MASK_ID1_CTRL

SWK_MASK_ID0_CTRL

SWK_DLC_CTRL

SWK_DATA7_CTRL

SWK_DATA6_CTRL

SWK_DATA5_CTRL

SWK_DATA4_CTRL

SWK_DATA3_CTRL

SWK_DATA2_CTRL

SWK_DATA1_CTRL

SWK_DATA0_CTRL

SWK_CAN_FD_CTRL

SWK_OSC_TRIM_CTRL

SWK_OPT_CTRL

SWK_OSC_CAL_H_STAT

SWK_OSC_CAL_L_STAT

SWK_CDR_CTRL1

SWK_CDR_CTRL2

SWK_CDR_LIMIT_HIGH

SWK_CDR_LIMIT_LOW

SUP_STAT_2

SUP_STAT_1

THERM_STAT

DEV_STAT

BUS_STAT_1

BUS_STAT_2

WK_STAT_1

WK_STAT_2

WK_LVL_STAT

HS_OC_OT_STAT

HS_OL_STAT

SWK_STAT

SWK_ECNT_STAT

SWK_CDR_STAT1

SWK_CDR_STAT2

FAM_PROD_STAT

Data Bit 15â¦8

CONTROL REGISTERS

MODE_1

MODE_0

reserved SOFT_RESET_RO

CHECKSUM WD_STM_EN_0

reserved

TIMER2_WK_EN TIMER1_WK_EN

INT_GLOBAL

reserved

TIMER1_ON_2

reserved

TIMER2_ON_2

reserved

HS_OV_SD_EN

reserved

HS2_2

reserved

HS4_2

FO_DC_1

FO_DC_0

PWM1_DC_7

PWM1_DC_6

PWM2_DC_7

PWM2_DC_6

reserved

SYS_STAT_7 SYS_STAT_6

reserved

FO_ON

WD_WIN

reserved

I_PEAK_TH

reserved

WK_MEAS

WK3_PUPD_1

WK3_FLT_1

TIMER1_ON_1

TIMER2_ON_1

HS_UV_SD_EN

HS2_1

HS4_1

GPIO2_2

PWM1_DC_5

PWM2_DC_5

reserved

SYS_STAT_5

VCC2_ON_1

reserved

WD_EN_WK_BUS

reserved

WK3_PUPD_0

WK3_FLT_0

TIMER1_ON_0

TIMER2_ON_0

HS_OV_UV_REC

HS2_0

HS4_0

GPIO2_1

PWM1_DC_4

PWM2_DC_4

reserved

SYS_STAT_4

VCC2_ON_0

reserved

WK2_PUPD_1

WK2_FLT_1

reserved

GPIO2_0

PWM1_DC_3

PWM2_DC_3

reserved

SYS_STAT_3

VCC1_OV_RST

reserved

WD_TIMER_2

CAN_2

reserved

WD_STM_EN_1

WK3_EN

WK2_PUPD_0

WK2_FLT_0

TIMER1_PER_2

TIMER2_PER_2

reserved

HS1_2

HS3_2

GPIO1_2

PWM1_DC_2

PWM2_DC_2

PWM2_FREQ_0

SYS_STAT_2

VCC1_RT_1

reserved

WD_TIMER_1

CAN_1

reserved

WK2_EN

WK1_PUPD_1

WK1_FLT_1

TIMER1_PER_1

TIMER2_PER_1

reserved

HS1_1

HS3_1

GPIO1_1

PWM1_DC_1

PWM2_DC_1

reserved

SYS_STAT_1

VCC1_RT_0

CFG

WD_TIMER_0

CAN_0

reserved

WK1_EN

WK1_PUPD_0

WK1_FLT_0

TIMER1_PER_0

TIMER2_PER_0

reserved

HS1_0

HS3_0

GPIO1_0

PWM1_DC_0

PWM2_DC_0

PWM1_FREQ_0

SYS_STAT_0

OSC_CAL

TBIT_7

reserved

ID28

ID20

ID12

reserved

MASK_ID28

MASK_ID20

MASK_ID12

reserved

DATA7_7

DATA6_7

DATA5_7

DATA4_7

DATA3_7

DATA2_7

DATA1_7

DATA0_7

reserved

TRIM_EN_1

TBIT_6

reserved

ID27

ID19

ID11

ID4

MASK_ID27

MASK_ID19

MASK_ID11

MASK_ID4

reserved

DATA7_6

DATA6_6

DATA5_6

DATA4_6

DATA3_6

DATA2_6

DATA1_6

DATA0_6

reserved

SELECTIVE WAKE REGISTERS

TRIM_EN_0

TBIT_5

SP_5

ID26

ID18

ID10

ID3

MASK_ID26

MASK_ID18

MASK_ID10

MASK_ID3

reserved

DATA7_5

DATA6_5

DATA5_5

DATA4_5

DATA3_5

DATA2_5

DATA1_5

DATA0_5

DIS_ERR_CNT

CANTO_MASK

TBIT_4

SP_4

ID25

ID17

ID9

ID2

MASK_ID25

MASK_ID17

MASK_ID9

MASK_ID2

reserved

DATA7_4

DATA6_4

DATA5_4

DATA4_4

DATA3_4

DATA2_4

DATA1_4

DATA0_4

RX_FILT_BYP

reserved

TBIT_3

SP_3

ID24

ID16

ID8

ID1

MASK_ID24

MASK_ID16

MASK_ID8

MASK_ID1

DLC_3

DATA7_3

DATA6_3

DATA5_3

DATA4_3

DATA3_3

DATA2_3

DATA1_3

DATA0_3

FD_FILTER_2

reserved

TBIT_2

SP_2

ID23

ID15

ID7

ID0

MASK_ID23

MASK_ID15

MASK_ID7

MASK_ID0

DLC_2

DATA7_2

DATA6_2

DATA5_2

DATA4_2

DATA3_2

DATA2_2

DATA1_2

DATA0_2

FD_FILTER_1

reserved

TBIT_1

SP_1

ID22

ID14

ID6

RTR

MASK_ID22

MASK_ID14

MASK_ID6

reserved

DLC_1

DATA7_1

DATA6_1

DATA5_1

DATA4_1

DATA3_1

DATA2_1

DATA1_1

DATA0_1

FD_FILTER_0

CFG_VAL

TBIT_0

SP_0

ID21

ID13

ID5

IDE

MASK_ID21

MASK_ID13

MASK_ID5

reserved

DLC_0

DATA7_0

DATA6_0

DATA5_0

DATA4_0

DATA3_0

DATA2_0

DATA1_0

DATA0_0

CAN_FD_EN

TRIM_OSC_7

RX_WK_SEL

OSC_CAL_H_7

OSC_CAL_L_7

reserved

CDR_LIM_H_7

CDR_LIM_L_7

SELECTIVE WAKE TRIM &CONFIGURATIONS REGISTERS

TRIM_OSC_6

reserved

OSC_CAL_H_6

OSC_CAL_L_6

reserved

CDR_LIM_H_6

CDR_LIM_L_6

TRIM_OSC_5

reserved

OSC_CAL_H_5

OSC_CAL_L_5

reserved

CDR_LIM_H_5

CDR_LIM_L_5

TRIM_OSC_4

TRIM_OSC_12

OSC_CAL_H_4

OSC_CAL_L_4

reserved

CDR_LIM_H_4

CDR_LIM_L_4

TRIM_OSC_3

TRIM_OSC_11

OSC_CAL_H_3

OSC_CAL_L_3

SELFILT_1

reserved

CDR_LIM_H_3

CDR_LIM_L_3

TRIM_OSC_2

TRIM_OSC_10

OSC_CAL_H_2

OSC_CAL_L_2

SELFILT_0

reserved

CDR_LIM_H_2

CDR_LIM_L_2

TRIM_OSC_1 TRIM_OSC_0

TRIM_OSC_9 TRIM_OSC_8

OSC_CAL_H_1 OSC_CAL_H_0

OSC_CAL_L_1 OSC_CAL_L_0

reserved

CDR_EN

SEL_OSC_CLK_1 SEL_OSC_CLK_0

CDR_LIM_H_1 CDR_LIM_H_0

CDR_LIM_L_1 CDR_LIM_L_0

reserved

POR

reserved

DEV_STAT_1

reserved

SBC_DEV_LVL

reserved

VS_UV

VSHS_UV

reserved

DEV_STAT_0

reserved

CFGP

reserved

VSHS_OV

reserved

CAN_WU

GPIO2_WU

GPIO2_LVL

reserved

STATUS REGISTERS

reserved

VCC2_OT

reserved

CANTO

reserved

TIMER_WU

GPIO1_WU

GPIO1_LVL

reserved

VCC2_UV

reserved

WD_FAIL_1

SYSERR

reserved

HS4_OC_OT

HS4_OL

reserved

VCC1_SC

TSD2

WD_FAIL_0

CAN_FAIL_1

reserved

WK3_WU

reserved

WK3_LVL

HS3_OC_OT

HS3_OL

VCC1_OV

VCC1_UV_FS

TSD1

SPI_FAIL

CAN_FAIL_0

reserved

WK2_WU

reserved

WK2_LVL

HS2_OC_OT

HS2_OL

VCC1_WARN

VCC1_UV

TPW

FAILURE

VCAN_UV

reserved

WK1_WU

reserved

WK1_LVL

HS1_OC_OT

HS1_OL

reserved

N_AVG_11

N_AVG_3

SYNC

reserved

N_AVG_10

N_AVG_2

SELECTIVE WAKE STATUS REGISTERS

reserved

ECNT_5

N_AVG_9

N_AVG_1

reserved

ECNT_4

N_AVG_8

N_AVG_0

CANSIL

ECNT_3

N_AVG_7

reserved

SWK_SET

ECNT_2

N_AVG_6

reserved

WUP

ECNT_1

N_AVG_5

reserved

WUF

ECNT_0

N_AVG_4

reserved

FAM_3

FAM_2

F A M I LY A N D P R O D U C T R E G I S T E R S

FAM_1

FAM_0

PROD_3

PROD_2

PROD_1

PROD_0

Access

Mode

read/write

read

read/write

read/clear

read

read/clear

read

6...0

Address

A6â¦A0

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001100

0001101

0010000

0010100

0010101

0010111

0011000

0011001

0011100

0011110

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1010100

1010101

1110000

1110001

1110010

1110011

1111110

Figure 50 TLE9260-3QX SPI Bit Mapping including Selective Wake

Data Sheet

117

Rev. 1.1, 2014-09-26

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