TLE9221SX Datasheet, PDF (13/91 Pages) Infineon Technologies AG – FlexRay Transceiver

TLE9221SX
Overview Functional Blocks
The logical I/O levels of all three digital pins are adapted to the reference voltage uV_IO. In case uV_IO is not available
or in an undervoltage condition, the RxD output is set to logical “low” and the input pins TxD and TxEN are set to
their default condition (see Table 2).
The Communication Controller logic block handles the interlock between TxD and TxEN. The Central State
Machine provides the interface to other TLE9221SX function blocks and handles the dependency based on the
selected mode of operation (see Figure 6).
Central
State
Machine
uV_IO
TxD
Transmitter
uV_IO
TxEN
Receiver
uV_IO
RxD
Figure 6 Block diagram of the Communication Controller Interface
The TxD input of the Communication Controller Interface is active only when the Transmitter is activated. To
activate the Transmitter, the transceiver TLE9221SX needs to be in BD_Normal mode, the TxEN input must be at
logical “low” and the BGE input pin must be at logical “high” (see Table 4).
The FlexRay transceiver shall never start data transmission with the communication element “Data_1”. Therefore,
the activation of the Transmitter via the TxEN signal is only possible while the TxD signal is at logical “low” (see
Figure 7).
While the Transmitter is enabled, the Communication Controller Interface drives the serial digital data stream
available at the TxD input pin to the FlexRay bus via the Transmitter. A logical “high” signal at the TxD pin drives
a “Data_1” signal to the FlexRay bus and a logical “low” signal drives a “Data_0” signal (see Table 4).
Data Sheet
13
Rev. 1.10, 2013-07-15