ICS8430S10I-03 Datasheet, PDF (8/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 4F. LVPECL DC Characteristics, V_DD = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
I_IH
I_IL
V_PP
V_CMR
V_OH
V_OL
V_SWING
Input High Current PCLK, nPCLK
Input Low Current
PCLK
nPCLK
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
Output High Voltage; NOTE 2
Output Low Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
V_DD = V_IN = 3.465V
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-10
-150
0.3
GND + 1.5
V_DD – 1.4
V_DD – 2.0
0.6
NOTE 1: Common mode input voltage is defined as V_IH.
NOTE 2: Outputs terminated with 50Ω to V_DD – 2V.
Typical
Maximum
150
1.0
V_DD
V_DD – 0.9
V_DD – 1.7
1.0
Units
µA
µA
µA
V
V
V
V
V
Table 4G. LVDS DC Characteristics, V_DD = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
V_OD
∆V_OD
V_OS
∆V_OS
Differential Output Voltage
V_OD Magnitude Change
Offset Voltage
V_OS Magnitude Change
Minimum
300
1.04
Typical
1.14
Maximum
600
50
1.24
50
Units
mV
mV
V
mV
Table 5. Crystal Characteristics
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
Units
MHz
Ω
pF
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
8
©2011 Integrated Device Technology, Inc.