ICS8430S10I-03 Datasheet, PDF (26/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 8.
V_DD
Q1
V_OUT
RL
50Ω
V_DD - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
V_DD – 2V.
• For logic high, V_OUT = V_{OH_MAX} = V_{DD_MAX} – 0.9V
(V_{DD_MAX} – V_{OH_MAX}) = 0.9V
• For logic low, V_OUT = V_{OL_MAX} = V_{DD_MAX} – 1.7V
(V_{DD_MAX} – V_{OL_MAX}) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V_{OH_MAX} – (V_{DD_MAX} – 2V))/R_L] * (V_{DD_MAX} – V_{OH_MAX}) = [(2V – (V_{DD_MAX} – V_{OH_MAX}))/R_L] * (V_{DD_MAX} – V_{OH_MAX}) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V_{OL_MAX} – (V_{DD_MAX} – 2V))/R_L] * (V_{DD_MAX} – V_{OL_MAX}) = [(2V – (V_{DD_MAX} – V_{OL_MAX}))/R_L] * (V_{DD_MAX} – V_{OL_MAX}) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.