ICS8430S10I-03 Datasheet, PDF (3/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
1, 13, 23
2
Name
V_DD
nOE_D
Type
Power
Input Pulldown
3, 12, 30, 31,
39, 42, 46
GND
4
nPLL_SEL
5,
XTAL_IN,
6
XTAL_OUT
7
nXTAL_SEL
Power
Input
Input
Input
Pulldown
Pulldown
8
PCLK
Input Pulldown
9
nPCLK
Input
Pullup/
Pulldown
10
nOE_C
Input Pulldown
11
14
15,
16
17,
18
19,
20
21, 22
24
25, 28
26, 27
29
nOE_B
Input Pulldown
nOE_A
SPI_SEL1,
SPI_SEL0
PCI_SEL1,
PCI_SEL0
DDR_SEL1,
DDR_SEL0
nQA, QA
V_DDA
V_{DDO_B}
QB1, QB0
Input
Input
Input
Input
Output
Power
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
nOE_REF
Input Pulldown
32
CORE_SEL Input Pulldown
33, 34
QD1, QD0 Output
35
QC
Output
36
V_{DDO_CD}
Power
Pin descriptions continue on the next page.
Description
Core supply pins.
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Power supply ground.
PLL bypass. When LOW, PLL is enabled. When HIGH, PLL is bypassed.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Selects XTAL input when LOW. Selects differential clock (PCLK, nPCLK) input
when HIGH. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V_DD/2.
Active LOW output enable for Bank C output. When logic HIGH, the output is high
impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL
interface levels.
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
Selects the SPI PLL clock reference frequency. See Table 3D.
Selects the PCI, PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
Differential output pair. Selectable between LVPECL and LVDS interface levels.
Analog supply pin.
Bank B output supply pins. 3.3 V or 2.5V supply.
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.
Active LOW output enabled. When logic HIGH, the QREF[2:0] outputs are high
impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled.
LVCMOS/ LVTTL interface levels.
Selects the processor core clock output frequency. The output frequency is 50MHz
when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL
interface levels.
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.
Single-end Bank C output. LVCMOS/LVTTL interface levels.
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
3
©2011 Integrated Device Technology, Inc.