ICS8430S10I-03 Datasheet, PDF (4/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Number
37
38
40
41, 48
43,
44,
45
47
Name
V_{DDO_E}
QE
nLVDS_SEL
V_{DDO_REF}
QREF2,
QREF1,
QREF0
nOE_E
Type
Power
Output
Input Pulldown
Power
Description
Bank E output supply pin. 3.3 V or 2.5V supply.
Single-end Bank E output. LVCMOS/LVTTL interface levels.
Selects between LVDS and LVPECL interface levels on differential output pair QA
and nQA. When LOW, LVDS levels are selected. When HIGH, LVPECL levels are
selected. See Table 3E.
Bank QREF output supply pins. 3.3 V or 2.5V supply.
Output
Single-ended reference clock outputs. LVCMOS/LVTTL interface levels.
Input
Pulldown
Active LOW output enable for Bank E output. When logic HIGH, the output is high
impedance (HI-Z). When logic LOW, the output is enabled. LVCMOS/LVTTL
interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
C_IN
C_PD
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
R_PULLUP
R_PULLDOWN
R_OUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
QB[0:1], QC,
QD[0:1], QE
QREF[0:2]
Test Conditions
V_DD, V_{DDO_X} = 3.465V
V_DD = 3.465V, V_{DDO_X} = 2.625V
V_{DDO_X} = 3.465V
V_{DDO_X} = 2.625V
NOTE: V_{DDO_X} denotes V_{DDO_B}, V_{DDO_CD}, V_{DDO_E} and V_{DDO_REF.}
Minimum
Typical
2
10
10
51
51
23
26
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
Ω
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
4
©2011 Integrated Device Technology, Inc.