ICS8430S10I-03 Datasheet, PDF (14/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
Parameter Measurement Information, continued
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Reference Point
(Trigger Edge)
Period Jitter, Peak-to-Peak
V_OH
V_REF
V_OL
t jit (pk-pk)
Histogram
Mean Period
(First edge after trigger)
10,000 cycles
nQA
QA
t half period n ➤ t half period n + 1 ➤
1
➤
f_o
t jit(hper) = t half period n — ¹
2*f_o
Half Period Jitter
nQA
QA
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Differential Output Duty Cycle/Pulse Width/Period
QBx, QC,
QDx, QE,
QREFx
t _PW
V
DDO_X
2
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
LVCMOS Output Duty Cycle/Pulse Width/Period
Phase Noise Plot
f₁ ^{Offset Frequency} f₂
RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers
RMS Phase Jitter
QREF{0:2]
V_{DDO_X}
2
QREF{0:2]
V_{DDO_X}
2
t sk(b)
LVCMOS Bank Skew
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
14
©2011 Integrated Device Technology, Inc.