ICS8430S10I-03 Datasheet, PDF (18/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω. By overdriving
the crystal oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
VCC
R1
100
Ro
Rs
Zo = 50 ohms
R2
Zo = Ro + Rs
100
LVCMOS Driver
XTAL_OUT
C1
XTAL_IN
.1uf
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
Zo = 50 ohms
Zo = 50 ohms
LVPECL Driver
R1
R2
50
50
R3
50
C2
XTAL_IN
.1uf
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
18
©2011 Integrated Device Technology, Inc.