ICS8430S10I-03 Datasheet, PDF (21/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
Application Schematic
Figure 7 shows an example of ICS8430S10I-03 application
schematic. In this example, the device is operated at V_DD = V_DDA =
V_{DDO_B} = V_{DDO_CD} = V_{DDO_E} = V_{DDO_REF} = 3.3V. An 18pF parallel
resonant 25MHz crystal is used. The load capacitance C1 = 18pF
and C2 = 18pF are recommended for frequency accuracy.
Depending on the parasitics of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will require adjusting C1 and C2. For this device, the
crystal load capacitors are required for proper operation.
CLOCK GENERATOR FOR CAVIUM PROCESSORS
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS8430S10I-03 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDDO_REF
U1
VDD
C1
18pF
X1
25MH₁ z_{8 p F}
C2
18pF
VDD
R3
R4
125
125
nOE_D
nPLL_SEL
XTAL_IN
XTAL_OUT
nXTAL_SEL
nOE_C
nOE_B
1
2
VDD
3
4
5
6
nOE_D
GND
nPLL_SEL
XTAL_IN
7 ^XTAL_OUT
8
9
10
11
12
nXTAL_SEL
PCLK
nPCLK
nOE_C
nOE_B
GND
Zo = 50
Zo = 50
LVPECL Driv er
CLK
nCLK
R7
R8
84
84
nOE_A
SPI_SEL1
SPI_SEL0
PCI_SEL1
PCI_SEL0
DDR_SEL1
DDR_SEL0
3.3V
BLM18BB221SN1
1
2 VDDO_REF (U1:41) (U1:48)
VDDO_REF
C5
0.1uF
Ferrite Bead C6
C7
10uF 0.1uF
C8
0.1uF
3.3V
BLM18BB221SN2
1
2 VDD
(U1:1) (U1:13) (U1:23) VDD
C9
0.1uF
Ferrite Bead C10
C11 C12 C13
10uF 0.1uF 0.1uF 0.1uF
3.3V
BLM18BB221SN3
1
2 VDDO (U1:25) (U1:28) (U1:36) (U1:37) VDDO
C14
0.1uF
Ferrite Bead C15
C16 C17
10uF 0.1uF 0.1uF
C18 C19
0.1uF 0.1uF
R1
QREF0
27
Zo = 50
VDDO
Receiv er
R2
QE
27
Zo = 50
Receiv er
VDDO_CD
36
35
QC
QD0
QD1
CORE_SEL
34
33
32
31
GND ₃₀
GND
nOE_REF
VDDO_B
QB0
QB1
VDDO_B
29
28
27
26
25
CORE_SEL
nOE_REF
VDD= VDDO_B = 3.3V
VDDO_CD = VDDO_E= VDDO_REF = 3.3V
3.3V
C3
0.01u
VDDA
VDD
R9 10
C4
10u
R5
133
Zo = 50 Ohm
QA0
nQA0
Zo = 50 Ohm
R10
82.5
LVPECL
Termination
R6
133
+
-
R11
82.5
QA0
nQA0
Zo = 50 Ohm
QA0
+
R12
Zo = 50 Ohm
100
nQA0
-
LVDS
Termination
Figure 7. ICS8430S10I-03 Schematic Example
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
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©2011 Integrated Device Technology, Inc.