ICS8430S10I-03 Datasheet, PDF (17/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
3.3V LVPECL Differential Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other
differential signals. The differential signals must meet the V_PP and
V_CMR input requirements. Figures 2A to 2E show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
3.3V
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
R5
100 - 200
R6
100 - 200
3.3V
R3
R4
84
84
C1
C2
R1
R2
125 125
3.3V
PCLK
nPCLK
LVPECL
Input
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
R3
125Ω
R4
125Ω
3.3V
PCLK
nPCLK
LVPECL
R1
R2
84Ω
84Ω
Input
Figure 2A. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 2B. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
3.3V
Zo = 50Ω
LVDS
Zo = 50Ω
R5
100Ω
3.3V
C1
C2
R1
R2
1k
1k
PCLK
VBB
nPCLK
LVPECL
Input
C3
0.1µF
Figure 2C. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
2.5V
SSTL
Zo = 60Ω
Zo = 60Ω
2.5V
R3
120Ω
R4
120Ω
3.3V
PCLK
R1
120Ω
R2
120Ω
nPCLK
LVPECL
Input
Figure 2D. PCLK/nPCLK Input Driven by a
3.3V SSTL Driver
3.3V
CML
Zo = 50Ω
Zo = 50Ω
3.3V
R1
R2
50Ω
50Ω
3.3V
PCLK
nPCLK
LVPECL
Input
Figure 2E. PCLK/nPCLK Input Driven by a CML Driver
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
17
©2011 Integrated Device Technology, Inc.