ICS8430S10I-03 Datasheet, PDF (10/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
133.33MHz; NOTE 6
30
ps
tjit(hper)
RMS Half-Period Jitter;
NOTE 2, 4
QA, nQA
100MHz; NOTE 7
133.33MHz; NOTE 8
100MHz; NOTE 9
30
ps
30
ps
30
ps
83.33MHz; NOTE 10
30
ps
QA, nQA
150
350
ps
t_R / t_F
Output Rise/Fall Time
QBx, QC,
QDx, QE,
10% to 90%
200
QREFx
900
ps
QA, nQA
48
52
%
odc
Output Duty Cycle
QBx, QC,
QE, QREFx
48
52
%
QDx
48
52
%
t_LOCK
Lock Time
55
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at maximum f_OUT, unless noted otherwise.
NOTE: All parameters are characterized using crystal input, unless noted otherwise.
NOTE: V_{DDO_X} denotes V_{DDO_B}, V_{DDO_CD,} V_{DDO_E} and V_{DDO_REF.}
NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V_{DDO_REF}/2.
NOTE 4: This parameter is measured at the crosspoint for differential and V_{DDO_X} /2 single-ended signals.
NOTE 5: Refer to the phase noise plot.
NOTE 6: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz.
NOTE 7: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = OFF, QDx = 100MHz, QE = OFF and QREFx = 25MHz.
NOTE 8: DDR_SEL[1:0] = 00: QA, nQA = 133.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz.
NOTE 9: DDR_SEL[1:0] = 01: QA, nQA = 100MHz, QBx = 50MHz, QC = 133.33MHz, QDx = OFF, QE = 125MHz and QREFx = 25MHz.
NOTE 10: DDR_SEL[1:0] = 10: QA, nQA = 83.33MHz, QBx = 50MHz, QC = OFF, QDx = 125MHz, QE = 125MHz and QREFx = 25MHz.
NOTE 11: This parameter is measured at 10K cycles.
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
10
©2011 Integrated Device Technology, Inc.