ICS8430S10I-03 Datasheet, PDF (22/31 Pages) Integrated Device Technology – Clock Generator for Cavium Processors

ICS8430S10I-03 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Considerations (LVCMOS/LVDS Outputs)
This section provides information on power dissipation and junction temperature for the ICS8430S10I-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430S10I-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V_DD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
• Power (core, LVDS) = V_{DD_MAX} * (I_DD + I_DDA) = 3.465V * (150mA + 20mA) = 589.05mW
LVCMOS Output Power Dissipation
• Dynamic Power Dissipation at 133.33MHz
Power (133.33MHz) = C_PD * Frequency * (V_DDO)² = 10pF * 133.33MHz * (3.465V)² = 16mW per output
Total Power (133.33MHz) = 16mW * 1 = 16mW
• Power(125MHz) = 10pF * 125MHz * (3.465V)² = 15mW per output
Total Power (125MHz) = 15mW * 3 = 45mW
• Dynamic Power Dissipation at 25MHz
Power (25MHz) = C_PD * Frequency * (V_DDO)² = 10pF * 25MHz * (3.465V)² = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
Power (50MHz) = C_PD * Frequency * (V_DDO)² = 10pF * 50MHz * (3.465V)² = 6mW per output
Total Power (50MHz) = 6mW * 2 = 12mW
Total Power Dissipation
• Total Power
= Power (core, LVDS) + Total Power (133.33MHz) + Total Power (125MHz) + Total Power (25MHz) + Total Power (50MHz)
= 589.05mW + 16mW + 45mW + 9mW + 12mW
= 671.05mW
ICS8430S10BYI-03 REVISION A FEBRUARY 22, 2011
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©2011 Integrated Device Technology, Inc.