ICS840N202I Datasheet, PDF (8/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
However, if operating in High Bandwidth Frequency Translation
mode, the PLL no longer has any frequency reference to use and
output stability is now determined by the stability of the internal VCO.
If the device is programmed to perform Manual switching, once the
selected input reference recovers, the ICS840N202I will switch back
to that input reference. If programmed for either Automatic mode, the
device will switch back to whichever input reference has a valid clock
first.
The switchover that results from returning from holdover or free-run
is handled in the same way as a switch between two valid input
references as described in the previous section.
Output Configuration
The two outputs of the ICS840N202I both provide the same clock
frequency. Both must operate from the same output voltage level of
3.3V or 2.5V, although this output voltage may be less than or equal
to the core voltage (3.3V or 2.5V) the rest of the device is operating
from. The output voltage level used on the two outputs is supplied on
the V_DDO pin.
The two outputs can be enabled individually via both register control
bits and input pins. When both the OEn register bit and OEn pin are
enabled, then the appropriate output is enabled. The OEn register
bits default to enabled so that by default the outputs can be directly
controlled by the input pins. Similarly, the input pins are provisioned
with weak pull-ups so that if they are left unconnected, the output
state can be directly controlled by the register bits. When the output
is in the disabled state, it will show a high impedance condition.
Serial Interface Configuration Description
The ICS840N202I has an I²C-compatible configuration interface to
access any of the internal registers (Table 4D) for frequency and PLL
parameter programming. The ICS840N202I acts as a slave device on
the I²C bus and has the address 0b11011xx, where xx is set by the
values on the S_A0 & S_A1 pins (see Table 4A for details). The
interface accepts byte-oriented block write and block read
operations. An address byte (P) specifies the register address (Table
4D) as the byte position of the first register to write or read. Data
bytes (registers) are accessed in sequential order from the lowest to
the highest byte (most significant bit first, see table 4B, 4C). Read
and write block transfers can be stopped after any complete byte
transfer. It is recommended to terminate I²C the read or write transfer
after accessing byte #23.
For full electrical I²C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK. The internal pull-up resistors
have a size of 50k typical.
Note: if a different device slave address is desired, please contact
IDT.
Table 4A. I²C Device Slave Address
1
1
0
1
1
S_A1 S_A0 R/W
Table 4B. Block Write Operation
Bit
1
2:8
9
10
Description
Slave
START Address
W (0)
ACK
Length (bits)
1
7
1
1
11:18
Address
Byte (P)
8
19
ACK
1
20:27
Data Byte
(P)
8
28
ACK
1
29-36 37
Data Byte
(P+1) ACK
8
1
...
Data Byte
...
8
...
ACK
1
...
STOP
1
Table 4C. Block Read Operation
Bit
1
2:8
9 10
Description
START
Slave
Address
W
(0)
A
C
K
Length (bits
1
7
1
1
11:18
Address
Byte (P)
8
19
20
21:27 28 29 30:37 38 39-46 47
...
... ...
A
C
K
Repeated Slave
START Address
R
(1)
A
C
K
Data Byte
(P)
A
C
K
Data Byte
(P+1)
A
C
K
Data Byte
...
A
C
K
STOP
1
1
7
11
8
1
8
1
8
1
1
ICS840N202CKI REVISION A NOVEMBER 1, 2013
8
©2013 Integrated Device Technology, Inc.