ICS840N202I Datasheet, PDF (2/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Complete Block Diagram
PLL_BYPASS
XTAL
XTAL_IN
XTA L_OUT
OSC
1
FemtoClock® NG
PD/LF
VCO
0
1995 - 2600 MHz
Feedback Divider
÷M_INT
[7:0]
÷M_FRAC
[17:0]
ADC
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
÷4
÷M1[16:0]
0
÷P[16:0]
1
POR
Control Logic
Global Registers
Register Set 0 0
Register Set 1 1
SCLK, S_A0, S_A1 SDATA CONFIG
PD/CP
Status Indicators
Output Divider
÷N[10:0]
Q0
OE0
Q1
OE1
LF1
R₃
C₃
LF0
R_S
C_P
C_S
CLK_ACTIVE
LOCK_IND
XTALBAD
CLK0BAD
CLK1BAD
HOLDOVER
ICS840N202CKI REVISION A NOVEMBER 1, 2013
2
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