ICS840N202I Datasheet, PDF (5/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Functional Description
The ICS840N202I is designed to provide two copies of almost any
desired output frequency within its operating range (0.98 - 250MHz)
from any input source in the operating range (8kHz - 710MHz). It is
capable of synthesizing frequencies from a crystal or crystal
oscillator source. The output frequency is generated regardless of
the relationship to the input frequency. The output frequency will be
exactly the required frequency in most cases. In most others, it will
only differ from the desired frequency by a few ppb. IDT configuration
software will indicate the frequency error, if any. The ICS840N202I
can translate the desired output frequency from one of two input
clocks. Again, no relationship is required between the input and
output frequencies in order to translate to the output clock rate. In this
frequency translation mode, a low-bandwidth, jitter attenuation option
is available that makes use of an external fixed-frequency crystal or
crystal oscillator to translate from a noisy input source. If the input
clock is known to be fairly clean or if some modulation on the input
needs to be tracked, then the high-bandwidth frequency translation
mode can be used, without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarm outputs are raised both as
register bits and hard-wired pins in the event of any
out-of-specification conditions arising. Clock switching is supported
in manual, revertive & non-revertive modes.
The ICS840N202I has two factory-programmed configurations that
may be chosen from as the default operating state after reset. This is
intended to allow the same device to be used in two different
applications without any need for access to the I²C registers. These
defaults may be over-written by I²C register access at any time, but
those over-written settings will be lost on power-down. Please
contact IDT if a specific set of power-up default settings is desired.
Configuration Selection
The ICS840N202I comes with two factory-programmed default
configurations. When the device comes out of power-up reset the
selected configuration is loaded into operating registers. The
ICS840N202I uses the state of the CONFIG pin or CONFIG register
bit (controlled by the CFG_PIN_REG bit) to determine which
configuration is active. When the output frequency is changed either
via the CONFIG pin or via internal registers, the output behavior may
not be predictable during the register writing and output settling
periods. Devices sensitive to glitches or runt pulses may have to be
reset once reconfiguration is complete.
Once the device is out of reset, the contents of the operating registers
can be modified by write access from the I²C serial port. Users that
have a custom configuration programmed may not require I²C
access.
It is expected that the ICS840N202I will be used almost exclusively
in a mode where the selected configuration will be used from device
power-up without any changes during operation. For example, the
device may be designed into a communications line card that
supports different I/O modules such as a standard OC-3 module
running at 155.52MHz or a (255/237) FEC rate OC-3 module running
at 167.332MHz. The different I/O modules would result in a different
level on the CONFIG pin which would select different divider ratios
within the ICS840N202I for the two different card configurations.
Access via I²C would not be necessary for operation using either of
the internal configurations.
Operating Modes
The ICS840N202I has three operating modes which are set by the
MODE_SEL[1:0] bits. There are two frequency translator modes -
low bandwidth and high bandwidth and a frequency synthesizer
mode. The device will operate in the same mode regardless of which
configuration is active.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
of the device.
Output Dividers & Supported Output Frequencies
In all 3 operating modes, the output stage behaves the same way, but
different operating frequencies can be specified in the two
configurations.
The internal VCO is capable of operating in a range anywhere from
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
the desired output frequency that results in a VCO operating
frequency within that range. The output divider stage N[10:0] is
limited to selection of even integers from 10 to 2046. Please refer to
Table 3 for the values of N applicable to the desired output frequency.
Table 3. Output Divider Settings & Frequency Ranges
Register
Setting
Nn[10:0]
Frequency
Divider
N
Minimum
f_OUT
(MHz)
Maximum
f_OUT
(MHz)
00000000000 -
0000000100x
2-8
Not Supported
0000000101x
10
199.5
260 (Note 1)
0000000110x
12
166.3
216.7
0000000111x
14
142.5
185.7
0000001000x
16
124.7
162.5
0000001001x
18
110.8
144.4
...
Even N
1995 / N
2600 / N
1111111111x
2046
0.98
1.27
Note 1: using a divider setting of N = 0x00A or 0x00B with a high
VCO frequency can result in the CMOS output running faster than its
250MHz maximum operating frequency.
Frequency Synthesizer Mode
This mode of operation allows an arbitrary output frequency to be
generated from a fundamental mode crystal input. As can be seen
from the block diagram in Figure 1, only the upper feedback loop is
used in this mode of operation.
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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©2013 Integrated Device Technology, Inc.