ICS840N202I Datasheet, PDF (23/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both V_SWING and V_OH must meet the V_PP and
V_CMR input requirements. Figures 6A to 6E show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 7A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
3.3V
LVPECL
Zo = 50Ω
Zo = 50Ω
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
R2
50Ω
Figure 6A. CLK/nCLK Input
Figure 6B. CLK/nCLK Input
Driven by an IDT Open Emitter LVHSTL Driver
Driven by a 3.3V LVPECL Driver
3.3V
LVPECL
3.3V
3.3V
CLK
nCLK
Differential
Input
3.3V
LVDS
Zo = 50Ω
Zo = 50Ω
3.3V
R1
100Ω
CLK
nCLK
Receiver
Figure 6C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
*R3
*R4
HCSL
3.3V
CLK
nCLK
Differential
Input
Figure 6D. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 6E. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
ICS840N202CKI REVISION A NOVEMBER 1, 2013
23
©2013 Integrated Device Technology, Inc.