ICS840N202I Datasheet, PDF (3/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1
2
3, 7, 13, 29
4
XTAL_IN
XTAL_OUT
V_DD
CLK_SEL
5
6
8, 21, 23, 27,
35
9
10
11, 32
CLK0
nCLK0
GND
CLK1
nCLK1
nc
12
PLL_BYPASS
14
SDATA
15
SCLK
16
CONFIG
17
18
19, 20
22
24
25
26
28
S_A1
S_A0
Rsvd
OE1
Q1
V_DDO
Q0
OE0
30
LOCK_IND
31
CLK_ACTIVE
Input
Power
Input
Input
Input
Power
Input
Input
Unused
Input
I/O
Input
Input
Input
Input
Reserved
Input
Output
Power
Output
Input
Output
Output
Pulldown
Pulldown
Pullup/
Pulldown
Crystal oscillator interface designed for 12pF parallel resonant crystals.
XTAL_IN (pin 1) is the input and XTAL_OUT (pin 2) is the output.
Core supply pins. All must be either 3.3V or 2.5V.
Input clock select. Selects the active differential clock input.
0 = CLK0, nCLK0 (default)
1 = CLK1, nCLK1
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating (set by the
internal pullup and pulldown resistors).
Power supply pins.
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Non-inverting differential clock input.
Inverting differential clock input. V_DD/2 default when left floating (set by the
internal pullup and pulldown resistors).
No connect. These pins are to be left unconnected.
Bypasses the VCXO PLL.
0 = PLL NOT bypassed (default)
1 = PLL Bypassed
I²C Data Input/Output. Open drain. LVCMOS/LVTTL Interface Levels.
I²C Clock Input. LVCMOS/LVTTL Interface Levels.
Configuration Pin. Selects between one of two factory programmable pre-set
power-up default configurations. The two configurations can have different
output/input frequency translation ratios, different PLL loop bandwidths, etc.
These default configurations can be overwritten after power-up via I²C if the
user so desires.
0 = Configuration 0 (default)
1 = Configuration 1
I²C Address Bit 1. LVCMOS/LVTTL Interface Levels.
I²C Address Bit 0. LVCMOS/LVTTL Interface Levels.
Reserved for future use. Should be left unconnected.
Active High Output Enable for Q1.
0 = Output pins high-impedance
1 = Output switching (default)
Clock output. LVCMOS/LVTTL Interface Levels.
Output supply voltage. Either 2.5V or 3.3V.
Clock output. LVCMOS/LVTTL Interface Levels.
Active High Output Enable for Q0.
0 = Output pins high-impedance
1 = Output switching (default)
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
Indicates which of the two differential clock inputs is currently selected.
0 - CLK0, nCLK0 differential input pair
1 - CLK1, nCLK1 differential input pair
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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©2013 Integrated Device Technology, Inc.