ICS840N202I Datasheet, PDF (6/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
The upper feedback loop supports a delta-sigma fractional feedback
divider. This allows the VCO operating frequency to be a non-integer
multiple of the crystal frequency. By using an integer multiple only,
lower phase noise jitter on the output can be achieved, however the
use of the delta-sigma divider logic will provide excellent
performance on the output if a fractional divisor is used.
Figure 1. Frequency Synthesizer Mode Block Diagram
High-Bandwidth Frequency Translator Mode
This mode of operation is used to translate one of two input clocks of
the same nominal frequency into an output frequency with little jitter
attenuation. As can be seen from the block diagram in Figure 2,
similarly to the Frequency Synthesizer mode, only the upper
feedback loop is used.
Low-Bandwidth Frequency Translator Mode
As can seen from the block diagram in Figure 3, this mode involves
two PLL loops. The lower loop with the large integer dividers is the
low bandwidth loop and it sets the output-to-input frequency
translation ratio.This loop drives the upper DCXO loop (digitally
controlled crystal oscillator) via an analog-digital converter.
PLL_BYPASS
XTAL
XTAL_IN
1
XTAL_OUT ^OSC
PD/LF
FemtoClock® NG
VCO
0
1995 - 2600 MHz
Output Divider
÷N[10:0]
Q0
OE0
Feedback Divider
÷M_INT
[7:0]
÷M_FRAC
[17:0]
Q1
OE1
ADC
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
÷4
÷M1[16:0]
0
÷P[16:0]
1
POR
Control Logic
Global Registers
Register Set 0 0
Register Set 1 1
SCLK, S_A0, S_A1 SDATA CONFIG
PD/CP
Status Indicators
LF1
R₃
C₃
LF0
R_S
C_P
CS
CLK_ACTIVE
LOCK_IND
XTALBAD
CLK0BAD
CLK1BAD
HOLDOVER
Figure 3. Low Bandwidth Frequency Translator Mode
Block Diagram
The phase detector of the lower loop is designed to work with
frequencies in the 8kHz - 16kHz range. The pre-divider stage is used
to scale down the input frequency by an integer value to achieve a
frequency in this range. By dividing down the fed-back VCO
operating frequency by the integer divider M1[18:0] to as close as
possible to the same frequency, very accurate output frequency
translations can be achieved.
Figure 2. High Bandwidth Frequency Translator Mode
Block Diagram
The input reference frequency range is now extended up to 710MHz.
A pre-divider stage P is needed to keep the operating frequencies at
the phase detector within limits.
Alarm Conditions & Status Bits
The ICS840N202I monitors a number of conditions and reports their
status via both output pins and register bits. All alarms will behave as
indicated below in all modes of operation, but some of the conditions
monitored have no valid meaning in some operating modes. For
example, the status of CLK0BAD, CLK1BAD and CLK_ACTIVE are
not relevant in Frequency Synthesizer mode. The outputs will still be
active and it is left to the user to determine which to monitor and how
to respond to them based on the known operating mode.
CLK_ACTIVE - indicates which input clock reference is being used to
derive the output frequency.
LOCK_IND - This status is asserted on the pin & register bit when the
PLL is locked to the appropriate input reference for the chosen mode
of operation. The status bit will not assert until frequency lock has
been achieved, but will de-assert once lock is lost.
XTALBAD - indicates if valid edges are being received on the crystal
input. Detection is performed by comparing the input to the feedback
signal at the upper loop’s Phase / Frequency Detector (PFD). If three
edges are received on the feedback without an edge on the crystal
input, the XTALBAD alarm is asserted on the pin & register bit. Once
an edge is detected on the crystal input, the alarm is immediately
deasserted.
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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