ICS840N202I Datasheet, PDF (7/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
CLK0BAD - indicates if valid edges are being received on the CLK0
reference input. Detection is performed by comparing the input to the
feedback signal at the appropriate Phase / Frequency Detector
(PFD). When operating in high-bandwidth mode, the feedback at the
upper PFD is used. In low-bandwidth mode, the feedback at the lower
PFD is used. If three edges are received on the feedback without an
edge on the divided down (÷P) CLK0 reference input, the CLK0BAD
alarm is asserted on the pin & register bit. Once an edge is detected
on the CLK0 reference input, the alarm is deasserted.
CLK1BAD - indicates if valid edges are being received on the CLK1
reference input. Behavior is as indicated for the CLK0BAD alarm, but
with the CLK1 input being monitored and the CLK1BAD output pin &
register bits being affected.
HOLDOVER - indicates that the device is not locked to a valid input
reference clock. This can occur in Manual switchover mode if the
selected reference input has gone bad, even if the other reference
input is still good. In automatic mode, this will only assert if both input
references are bad.
Input Reference Selection and Switching
When operating in Frequency Synthesizer mode, the CLK0 and
CLK1 inputs are not used and the contents of this section do not
apply. Except as noted below, when operating in either High or Low
Bandwidth Frequency Translator mode, the contents of this section
apply equally when in either of those modes.
Both input references CLK0 and CLK1 must be the same nominal
frequency. These may be driven by any type of clock source,
including crystal oscillator modules. A difference in frequency may
cause the PLL to lose lock when switching between input references.
Please contact IDT for the exact limits for your situation.
The global control bits AUTO_MAN[1:0] dictate the order of priority
and switching mode to be used between the CLK0 and CLK1 inputs.
Manual Switching Mode
When the AUTO_MAN[1:0] field is set to Manual via Pin, then the
ICS840N202I will use the CLK_SEL input pin to determine which
input to use as a reference. Similarly, if set to Manual via Register,
then the device will use the CLK_SEL register bit to determine the
input reference. In either case, the PLL will lock to the selected
reference if there is a valid clock present on that input.
If there is not a valid clock present on the selected input, the
ICS840N202I will go into holdover (Low Bandwidth Frequency
Translator mode) or free-run (High Bandwidth Frequency Translator
mode) state. In either case, the HOLDOVER alarm will be raised.
This will occur even if there is a valid clock on the non-selected
reference input.
The device will recover from holdover / free-run state once a valid
clock is re-established on the selected reference input.
The ICS840N202I will only switch input references on command from
the user. The user must either change the CLK_SEL register bit (if in
Manual via Register) or CLK_SEL input pin (if in Manual via Pin).
Automatic Switching Mode
When the AUTO_MAN[1:0] field is set to either of the automatic
selection modes (Revertive or Non-Revertive), the ICS840N202I
determines which input reference it prefers / starts from by the state
of the CLK_SEL register bit only. The CLK_SEL input pin is not used
in either Automatic switching mode.
When starting from an unlocked condition, the device will lock to the
input reference indicated by the CLK_SEL register bit. It will not pay
attention to the non-selected input reference until a locked state has
been achieved. This is necessary to prevent ‘hunting’ behavior during
the locking phase.
Once the ICS840N202I has achieved a stable lock, it will remain
locked to the preferred input reference as long as there is a valid clock
on it. If at some point, that clock fails, then the device will
automatically switch to the other input reference as long as there is a
valid clock there. If there is not a valid clock on either input reference,
the ICS840N202I will go into holdover (Low Bandwidth Frequency
Translator mode) or free-run (High Bandwidth Frequency Translator
mode) state. In either case, the HOLDOVER alarm will be raised.
The device will recover from holdover / free-run state once a valid
clock is re-established on either reference input. If clocks are valid on
both input references, the device will choose the reference indicated
by the CLK_SEL register bit.
If running from the non-preferred input reference and a valid clock
returns, there is a difference in behavior between Revertive and
Non-revertive modes. In Revertive mode, the device will switch back
to the reference indicated by the CLK_SEL register bit even if there
is still a valid clock on the non-preferred reference input. In
Non-revertive mode, the ICS840N202I will not switch back as long as
the non-preferred input reference still has a valid clock on it.
Switchover Behavior of the PLL
Even though the two input references have the same nominal
frequency, there may be minor differences in frequency and
potentially large differences in phase between them. The
ICS840N202I will adjust its output to the new input reference. It will
use Phase Slope Limiting to adjust the output phase at a fixed
maximum rate until the output phase and frequency are now aligned
to the new input reference. Phase will always be adjusted by
extending the clock period of the output so that no unacceptably short
clock periods are generated on the output ICS840N202I.
Holdover / Free-run Behavior
When both input references have failed (Automatic mode) or the
selected input has failed (Manual mode), the ICS840N202I will enter
holdover (Low Bandwidth Frequency Translator mode) or free-run
(High Bandwidth Frequency Translator mode) state . In both cases,
once both input references are lost, the PLL will stop making
adjustments to the output phase.
If operating in Low Bandwidth Frequency Translation mode, the PLL
will continue to reference itself to the local oscillator and will hold its
output phase and frequency in relation to that source. Output stability
is determined by the stability of the local oscillator in this case.
ICS840N202CKI REVISION A NOVEMBER 1, 2013
7
©2013 Integrated Device Technology, Inc.