ICS840N202I Datasheet, PDF (4/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 1. Pin Descriptions
Number
Name
Type
Description
33, 34
LF0, LF1
Input
Loop filter connection node pins. LF0 is the output. LF1 is the input.
36
V_DDA
Power
Analog supply voltage. See Applications section for details on how to connect
this pin.
37
HOLDOVER
Output
Alarm output reflecting if the device is in a holdover state. LVCMOS/LVTTL
interface levels.
0 = Device is locked to a valid input reference
1 = Device is not locked to a valid input reference
38
CLK0BAD
Output
Alarm output reflecting the state of CLK0. LVCMOS/LVTTL interface levels.
0 = Input Clock 0 is switching within specifications
1 = Input Clock 0 is out of specification
39
CLK1BAD
Output
Alarm output reflecting the state of CLK1. LVCMOS/LVTTL interface levels.
0 = Input Clock 1 is switching within specifications
1 = Input Clock 1 is out of specification
40
XTALBAD
Output
Alarm output reflecting the state of XTAL. LVCMOS/LVTTL interface levels.
0 = crystal is switching within specifications
1 = crystal is out of specification
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
C_IN
Input
Capacitance
XTAL_IN, XTAL_OUT,
PLL_BYPASS, CONFIG,
A0, A1, OE0, OE1, SCLK
C_PD
R_PULLUP
R_PULLDOWN
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Q0, Q1
R_OUT
Output
Impedance
CLK_ACTIVE,
HOLDOVER, XTALBAD,
CLK0BAD, CLK1BAD,
LOCK_IND
Test Conditions
Minimum Typical Maximum Units
4
pF
8
pF
51
k
51
k
15

25

ICS840N202CKI REVISION A NOVEMBER 1, 2013
4
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