ICS840N202I Datasheet, PDF (25/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Schematic Layout
Figure 8 (next page) shows an example of the ICS840N202I UFT
application schematic. Input and output terminations shown are
intended as examples only and may not represent the exact user
configuration. In this example, the device is operated at V_DD = 3.3V.
To use the 2.5V CMOS output option, please refer to the section
“Output Configuration”. A 12pF parallel resonant 16MHz to 40MHz
crystal is used in this example, though different crystal frequencies
may be used. The load capacitance C1= 5pF and C2 = 5pF are
recommended for frequency accuracy, but these may be adjusted for
different board layouts. If different crystal types are used, please
consult IDT for recommendations.
It is recommended that the loop filter components be laid out for the
3-pole option which can be adjusted for additional spur reduction and
also allow for a 2-pole filter by setting R3 to 0 ohms and not
populating C3.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS840N202I UFT provides
separate power supplies to isolate from coupling into the internal
PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set. the opposite side.
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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©2013 Integrated Device Technology, Inc.