ICS840N202I Datasheet, PDF (27/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS840N202I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS840N202I is the sum of the core power plus the power dissipated into the load.
The following is the power dissipation for V_DD= 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)_MAX = V_{DD_MAX} * (I_DD + I_DDO) + I_DDA = 3.465V * 320mA = 1108.8mW
LVCMOS Output Power Dissipation
• Output Impedance R_OUT Power Dissipation due to Loading 50 to V_DDO/2
Output Current I_OUT = V_{DDO_MAX} / [2 * (50 + R_OUT)] = 3.465V / [2 * (50 + 15)] = 26.65mA
• Power Dissipation on the R_OUT per LVCMOS output
Power (R_OUT) = R_OUT * (I_OUT)² = 15 * (26.65mA)² = 10.65mW per output
• Total Power (R_OUT) = 10.65mW * 2 = 21.3mW
Total Power Dissipation
• Total Power
= Power (core) + Total Power (R_OUT)
= 1108.8mW + 21.3mW = 1130.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = _JA * Pd_total + T_A
Tj = Junction Temperature
_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T_A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.4°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.130W * 32.4°C/W = 121.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 9. Thermal Resistance _JA for 40 Lead VFQFN, Forced Convection
_JA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
32.4°C/W
1
25.7°C/W
2.5
23.4°C/W
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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©2013 Integrated Device Technology, Inc.