ICS840N202I Datasheet, PDF (10/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
The register bits described in Table 4E are duplicated, with one set
applying for Configuration 0 and the other for Configuration 1. The
functions of the bits are identical, but only apply when the
configuration they apply to is enabled. Replace the lowercase n in the
bit field description with 0 or 1 to find the field’s location in the bitmap
in Table 4D.
Table 4E. Configuration-Specific Control Bits
Register Bits
Function
Pn[16:0]
Reference Pre-Divider for Configuration n.
M1_n[16:0]
Integer Feedback Divider in Lower Feedback Loop for Configuration n.
M_INTn[7:0]
Feedback Divider, Integer Value in Upper Feedback Loop for Configuration n.
M_FRACn[17:0] Feedback Divider, Fractional Value in Upper Feedback Loop for Configuration n.
Nn[10:0]
Output Divider for Configuration n.
BWn[6:0]
Internal Operation Settings for Configuration n.
Please use IDT ICS840N202I Configuration Software to determine the correct settings for these bits for the specific
configuration. Alternatively, please consult with IDT directly for further information on the functions of these bits.The
function of these bits is explained in Tables 4J and 4K.
Table 4F. Global Control Bits
Register Bits
Function
MODE_SEL[1:0]
PLL Mode Select
00 = Low Bandwidth Frequency Translator
01 = Frequency Synthesizer
10 = High Bandwidth Frequency Translator
11 = High Bandwidth Frequency Translator
CFG_PIN_REG
Configuration Control. Selects whether the configuration selection function is under pin or register control.
0 = Pin Control
1 = Register Control
CONFIG
Configuration Selection. Selects whether the device uses the register configuration set 0 or 1. This bit only has an
effect when the CFG_PIN_REG bit is set to 1 to enable register control.
OE0
Output Enable Control for Output 0. Both this register bit and the corresponding Output Enable pin OE0 must be
asserted to enable the Q0 output.
0 = Output Q0 disabled
1 = Output Q0 under control of the OE0 pin
OE1
Output Enable Control for Output 1. Both this register bit and the corresponding Output Enable pin OE1 must be
asserted to enable the Q1 output.
0 = Output Q1 disabled
1 = Output Q1 under control of the OE1 pin
Rsvd
Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed
AUTO_MAN[1:0]
Selects how input clock selection is performed.
00 = Manual Selection via pin only
01 = Automatic, non-revertive
10 = Automatic, revertive
11 = Manual Selection via register only
CLK_SEL
In manual clock selection via register mode, this bit will command which input clock is selected. In the automatic
modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.
0 = CLK0
1 = CLK1
ADC_RATE[1:0]
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the crystal input frequency.
00 = Crystal Frequency / 16
01 = Crystal Frequency / 8
10 = Crystal Frequency / 4 (recommended)
11 = Crystal Frequency / 2
LCK_WIN[1:0]
Sets the width of the window in which a new reference edge must fall relative to the feedback edge: 00 = 2usec
(recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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