ICS840N202I Datasheet, PDF (12/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 4K. Functions of Fields in BW[6:0]
Register Bits
Function
PLL2_LF[1:0]
Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes.
Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4L for settings.
DSM_ORD
Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation.
DSM_EN
Enables Delta-Sigma Modulator.
0 = Disabled - feedback in integer mode only
1 = Enabled - feedback in fractional mode
PLL2_CP[1:0]
Upper loop PLL charge pump current settings:
00 = 173A (defaults to this setting in Low Bandwidth Mode)
01 = 346A
10 = 692A
11 = reserved
PLL2_LOW_ICP
Reduces Charge Pump current by 1/3^RD to reduce bandwidth variations resulting from higher feedback register
settings or high VCO operating frequency (>2.4GHz).
ADC_GAIN[3:0] Gain setting for ADC in Low Bandwidth Mode.
PLL1_CP[1:0]
Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode):
00 = 800A
01 = 400A
10 = 200A
11 = 100A
Table 4L. Upper Loop (PLL2) Bandwidth Settings
Desired Bandwidth
PLL2_CP
PLL2ICP
Frequency Synthesizer Mode
200kHz
00
1
400kHz
01
1
800kHz
10
1
2MHz
10
1
High Bandwidth Frequency Translator Mode
200kHz
00
1
400kHz
01
1
800kHz
10
1
4MHz
10
0
Low Bandwidth Frequency Translator Mode
200kHz
00
PLL2_LF
00
01
10
11
00
01
10
11
00
NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz.
ICS840N202CKI REVISION A NOVEMBER 1, 2013
12
©2013 Integrated Device Technology, Inc.