ICS840N202I Datasheet, PDF (11/31 Pages) Integrated Device Technology – Fourth generation FemtoClock

ICS840N202I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 4G. Global Status Bits
Register Bits
Function
CLK0BAD
Status Bit for input clock 0. This function is mirrored in the CLK0BAD pin.
0 = input CLK0 is good
1 = input CLK0 is bad. Self clears when input clock returns to good status
CLK1BAD
Status Bit for input clock 1. This function is mirrored in the CLK1BAD pin.
0 = input CLK1 is good
1 = input CLK1 is bad. Self clears when input clock returns to good status
XTALBAD
Status Bit. This function is mirrored on the XTALBAD pin.
0 = crystal input good
1 = crystal input bad. Self-clears when the XTAL clock returns to good status
LOCK_IND
Status bit. This function is mirrored on the LOCK_IND pin.
0 = PLL unlocked
1 = PLL locked
HOLDOVER
Status Bit. This function is mirrored on the HOLDOVER pin.
0 = Input to phase detector is within specifications and device is tracking to it
1 = Phase detector input not within specifications and DCXO is frozen at last value
CLK_ACTIVE
Status Bit. Indicates which input clock is active. Automatically updates during fail-over switching. Status also
indicated on CLK_ACTIVE pin.
Table 4J. BW[6:0] Bits
Mode
BW[6]
Synthesizer Mode
PLL2_LF[1]
High-Bandwidth Mode PLL2_LF[1]
Low-Bandwidth Mode ADC_GAIN[3]
BW[5]
BW[4]
BW[3]
PLL2_LF[0] DSM_ORD
DSM_EN
PLL2_LF[0] DSM_ORD
DSM_EN
ADC_GAIN[2] ADC_GAIN[1] ADC_GAIN[0]
BW[2]
PLL2_CP[1]
PLL2_CP[1]
PLL1_CP[1]
BW[1]
PLL2_CP[0]
PLL2_CP[0]
PLL1_CP[0]
BW[0]
PLL2_LOW_ICP
PLL2_LOW_ICP
PLL2_LOW_ICP
ICS840N202CKI REVISION A NOVEMBER 1, 2013
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