82P33731_16 Datasheet, PDF (52/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
8.3.6
WIRING THE DIFFERENTIAL INPUT FOR SINGLE-
ENDED LEVELS
Figure 32 shows how a differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_CC/2 is gener-
ated by the bias resistors R1 and R2. The bypass capacitor (C1)
is used to help filter noise on the DC bias. This bias circuit should
be located as close to the input pin as possible. The ratio of R1
and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and V_CC = 3.3V, R1 and R2 value should be
adjusted to set V_REF at 1.25V. The values below are for when both
the single ended swing and V_CC are at the same voltage. This
configuration requires that the sum of the output impedance of the
driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V_IL cannot be less
than -0.3V and V_IH cannot be more than V_CC + 0.3V. Suggest
edge rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The data-
sheet specifications are characterized and guaranteed by using a
differential signal.
Figure 32. Recommended Schematic for Wiring a Differential Input to Accept Single-Ended Levels
Vth = VCC*[R2/(R1+R2)]
For the example in Figure 32, R1 = R2, so Vth = VCC/2 =1.65 V
The suggested single-ended signal input:
V_IHmax = VCC
V_ILmin = 0 V
V_swing = 0.6 V ~ VCC
DC offset (Swing Center) = Vth/2 +/- V_swing*10%
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Revision 5, December 8, 2016