82P33731_16 Datasheet, PDF (39/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
5.1.3
SUPPORTED TRANSACTIONS
The supported types of transactions are shown below.
Current Read
S
Dev Addr + R
A
Sequential Read
S
Dev Addr + W
A
Sequential Write
S
Dev Addr + W
A
Data 0
A
Data 1
A
A
Data n
A
P
Offset Addr
A
Sr
Dev Addr + R
A
Data 0
A
Data 1
A
A
Offset Addr
A
Data 0
A
Data 1
A
A
Data n
A
P
Data n
A
P
from master to slave
from slave to master
S = start
Sr= repeated start
A = acknowledge
A = not acknowledge
P = stop
Figure 17. I2C Slave Interface Supported Transactions
Table 15: Description of I2C Slave Interface Supported Transactions
Operation
Current Read
Sequential Read
Sequential Write
Description
Reads a burst of data from an internal determined starting address, this starting address is equal to the last address accessed
during the last read or write operation, incremented by one. If the address exceeds the address space, it will start from 0 again.
Reads a burst of data from a specified address space. The starting address of the space is specified as offset address.
Writes a burst of data to a specified address space, the starting address of the space is specified as offset address.
The registers are divided up into pages of 128 bytes with each byte
having a separate address. Multi-byte registers need to be accessed in
multiple read/write cycles. Address 0x7F is reserved for the page index
pointer.
All register accesses are done as 8 bit I2C cycles. The 8-bit address
refers to the register offset within the active page. If access to a different
page is needed then a separate I2C write must be performed to the
page register (0x7F). This makes the new page active and then 8 bit
reads and writes can be performed anywhere within that page.
Note that accesses to multi-byte registers should not be interrupted
by accesses to other addresses, because that may cause the data to be
corrupted. The access of the multi-byte registers is different from the sin-
gle-byte registers. Take the DPLL1 priority table registers (00H and 01H
in page 2) as an example, the write operation for the multi-byte registers
follows a fixed sequence. The register (00H) is configured first and the
register (01H) is configured last. The two registers are configured contin-
uously and should not be interrupted by any operation. The DPLL1 prior-
ity table configuration will take effect after all the two registers are
configured. During read operation, the register (00H) is read first and the
register (01H) is read last. The priority table configuration register read-
ing should be continuous and not be interrupted by any operation.
5.2 I2C MASTER MODE
The 82P33731 has the capability to read from an external I2C
EEPROM upon exit from reset. This reduces the start-up load on the
microprocessor by programming the registers in the device-address
space 101_0xx1 (registers in device-address space 101_0xx0 must still
be written by the microprocessor). This mode uses the MPU_MODE1/
I2CM_SCL and the MPU_MODE0/I2CM_SDA pins as the serial clock
and the serial data respectively, it requires that both these pins be pulled
high through resistors (these resistor values are dependent on the bus
capacitance and I2C speed of the application). Access to the 82P33731
registers through the microprocessor interface I2C serial port is not
available until the EEPROM reading process is completed.
As an I²C bus master, the 82P33731 will support the following:
• 8 kbit (1023 x 8) I2C EEPROM with device address 1010000 (for
the base block)
• Sequential read (block read) of the entire memory-map for device-
excluding APLL3, from byte-address 0x000 to 0x39E
• 7-bit device address mode
• Validation of the EEPROM read data via CCITT-8 CRC check
against value stored in memory-map address 0x39E
• Support for 100 kHz and 400 kHz operation with speed program-
mability. If bit 7 is set at memory-map address 0x001, the
82P33731 will shift from 100 kHz operation to 400 kHz operation.
• 2-byte word-addressing (1-byte word addressing is supported by
offsetting the memory-map upwards 1 address in the EEPROM)
• Read will abort with an alarm (RD_EEPROM_ERR interrupt status
set) if any of the following conditions occur: Slave NACK, CRC fail-
ure, Slave Response time-out
©2016 Integrated Device Technology, Inc.
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Revision 5, December 8, 2016