82P33731_16 Datasheet, PDF (40/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
As the 82P33731 I2C master bus is meant only to read from a single
EEPROM, it has the following restrictions:
• No support for Multi-master
• No support for Slave clock stretching
• No support for I2C Start Byte protocol
• No support for EEPROM Chaining
• No support for Writing to external I2C devices including the
EEPROM used for booting
5.2.1
I2C BOOT-UP INITIALIZATION MODE
EEPROM mode is enabled via setting the MPU_MODE[1:0] pins
high (through two separate pull-up resistors). Once the RSTB input has
been asserted (low) and then de-asserted (high) and the device internal
calibration has been completed, the 82P33731 will perform a short block
read at 100 kHz to program the EPROM read speed (100 kHz or 400
kHz). The 82P33731 will then perform a block read to program all the
device configuration registers, and check the CRC of the EEPROM
data. During the boot-up EEPROM-reading process, the 82P33731 will
not respond to microprocessor serial control port accesses. Once the
initialization process is completed, the contents of any of the device con-
figuration registers can be further altered by the microprocessor, if
desired.
The 82P33731 can work with EEPROMs supporting 2-byte word-
addresses or 1-byte word-addresses by using 2-byte word addressing
for both. This works in the usual manner for EEPROMs supporting 2-
byte word addresses, and gives an address-to-address match between
EEPROM and memory-map. For EEPROMs supporting only 1-byte
word addresses, the second address byte will cause an addition incre-
ment of the address counter, and the memory-map will be read at the
next highest EEPROM address,.i.e memory-map (CSR) address 0x00
will be read from EEPROM address 0x01, and memory map address
0x39E will be read from EEPROM address 0x39F.
If a NACK is received to any of the read cycles performed by the
82P33731 during the initialization process, or if the CRC does not match
the one stored in memory-map address 0x39E, the boot process will be
restarted. This restart can happen up to three times before an abort is
declared and the RD_EEPROM_ERR interrupt status bit is set. Also on
RD_EEPROM_ERR the MPU_MODE1/ I2CM_SCL and MPU_MODE0/
I2CM_SDA pins are both held low until the interrupt status bit is cleared
or the device is reset. The suggested method for dealing with RD_EE-
PROM_ERR is to externally set the MPU_MODE[1:0] pins to 00 and
then reset the 82P33731 so that it will boot into I2C serial port mode.
After a successful EEPROM boot, the 82P33731 will stop toggling
the MPU_MODE1/ I2CM_SCL and MPU_MODE0/I2CM_SDA pins,
returning them to static high values, and the RD_EEPROM_DONE inter-
rupt status bit will be set. The I2C serial port will now respond to micro-
processor reads and writes to the appropriate I2C device address.
5.2.2
EEPROM MEMORY MAP NOTES
The EEPROM memory-map is the same as the control and status
register (CSR) map with the following additions and constraints:
1. For EEPROMs supporting 2-byte word-address, the memory-map
addresses are the same as the EPPROM addresses; for EEPROMs
supporting 1-byte word-address, the memory-map addresses will by
mapped to the next address in the EEPROM, i.e. memory-map address
0x00 will be read from EEPROM address 0x01, and memory-map
address 0x39E will be read from EEPROM address 0x39F.
2. Memory-map address 0x001, bit 7 is the EEPROM read speed (0
for 100 kps, 1 for 400 kbps)
3. Memory-map address 0x39E is the CRC-8 of the memory-map
from 0x000 to 0x39D (the standard CCITT CRC-8 with the data width
and result width being 8; the polynomial is (0, 1, 2, 8) or "0x07"). NB: all
memory-map addresses from 0x000 to 0x39d are included in the
sequential calculation of CRC, including those not used in the CSR - it is
recommend that data at unused addresses be set to 0x00.
4. Memory-map addresses 0x392 to 0x39D must be set to the default
values shown in the CSR documentation.
5. The device address at memory-map address 0x00f must match
the address set by the board.
6. Each memory-map address that is a multiple of 0x7F must contain
the pointer to the next page of the CSR i.e
0x07f 0x01
0x0ff 0x02
0x17f 0x03
0x1ff 0x04
0x27f 0x05
0x2ff 0x06
0x37f 0x07
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Revision 5, December 8, 2016