82P33731_16 Datasheet, PDF (4/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
3.2.6 APLL3 .............................................................................................................................................................................................. 30
3.2.6.1 External Crystals .............................................................................................................................................................. 30
3.2.7 Output Clocks & Frame Sync Signals .......................................................................................................................................... 31
3.2.7.1 Output Clocks ................................................................................................................................................................... 31
3.2.7.2 Frame Sync Signals ......................................................................................................................................................... 32
3.2.8 Input and output Phase control .................................................................................................................................................... 34
3.2.8.1 DPLL1 and DPL2 Phase offset control ............................................................................................................................. 34
3.2.8.2 Input Phase control .......................................................................................................................................................... 34
3.2.8.3 Output Phase control ........................................................................................................................................................ 34
4 POWER SUPPLY FILTERING TECHNIQUES ................................................................................................................. 35
5 MICROPROCESSOR INTERFACE .................................................................................................................................. 37
5.1 I2C SLAVE MODE ......................................................................................................................................................................................... 37
5.1.1 I2C Device Address ........................................................................................................................................................................ 37
5.1.2 I2C Bus Timing ............................................................................................................................................................................... 37
5.1.3 Supported Transactions ................................................................................................................................................................ 39
5.2 I2C MASTER MODE ..................................................................................................................................................................................... 39
5.2.1 I2C Boot-up Initialization Mode ..................................................................................................................................................... 40
5.2.2 EEPROM memory map notes ........................................................................................................................................................ 40
6 JTAG ................................................................................................................................................................................ 41
7 THERMAL MANAGEMENT ............................................................................................................................................. 42
7.1 JUNCTION TEMPERATURE ........................................................................................................................................................................ 42
7.2 THERMAL RELEASE PATH ......................................................................................................................................................................... 42
8 ELECTRICAL SPECIFICATIONS .................................................................................................................................... 43
8.1 ABSOLUTE MAXIMUM RATING .................................................................................................................................................................. 43
8.2 RECOMMENDED OPERATION CONDITIONS ............................................................................................................................................ 43
8.3 I/O SPECIFICATIONS ................................................................................................................................................................................... 44
8.3.1 AMI Input / Output Port .................................................................................................................................................................. 44
8.3.1.1 Structure ........................................................................................................................................................................... 44
8.3.1.2 I/O Level ........................................................................................................................................................................... 44
8.3.1.3 Over-Voltage Protection ................................................................................................................................................... 45
8.3.2 CMOS Input / Output Port .............................................................................................................................................................. 45
8.3.3 LVPECL / LVDS Input / Output Port .............................................................................................................................................. 46
8.3.3.1 PECL Input Port ............................................................................................................................................................... 46
8.3.3.2 LVPECL Output Port .................................................................................................................................................... 47
8.3.3.2.1 LVPECL Termination for 3.3 V ...................................................................................................................... 47
8.3.3.2.2 LVPECL Termination for 2.5 V ...................................................................................................................... 48
8.3.4 LVDS Input / Output Port ............................................................................................................................................................... 49
8.3.4.1 LVDS Input Port ............................................................................................................................................................... 49
8.3.4.2 LVDS Output Port ............................................................................................................................................................. 50
8.3.5 Output Clock Duty Cycle ............................................................................................................................................................... 51
8.3.6 Wiring the Differential Input for Single-Ended Levels ................................................................................................................ 52
8.4 JITTER PERFORMANCE .......................................................................................................................................................................... 53
8.5 INPUT / OUTPUT CLOCK TIMING ............................................................................................................................................................... 64
8.6 OUTPUT / OUTPUT CLOCK TIMING ........................................................................................................................................................... 64
PACKAGE DIMENSIONS ..................................................................................................................................................... 65
ORDERING INFORMATION.................................................................................................................................................. 67
REVISION HISTORY ............................................................................................................................................................. 67
©2016 Integrated Device Technology, Inc.
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Revision 5, December 8, 2016