82P33731_16 Datasheet, PDF (29/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
The DPLL locking status is indicated by the corresponding
DPLL_LOCK bits and by the DPL_LOCK pins.
3.2.4.5 Phase Lock Alarm
DPLL1 have a phase lock alarm that will be raised when the selected
input clock can not be locked in DPLL1 within a certain period. This
period can be calculated as follows:
Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]
The phase lock alarm is indicated by the corresponding
INn_PH_LOCK_ALARM bit (14  n  1).
The phase lock alarm can be cleared, as selected by the
PH_ALARM_TIMEOUT bit:
• It is cleared when a ‘1’ is written to the corresponding
INn_PH_LOCK_ALARM bit;
• It is cleared after the period (= TIME_OUT_VALUE[5:0] X MUL-
TI_FACTOR[1:0] in second) starting from the time the alarm is
raised.
The selected input clock with a phase lock alarm is disqualified for
the DPLL1 to lock.
Note that phase lock alarm is not available for DPLL2.
3.2.5 APLL1 AND APLL2
APLL1 and APLL2 are provided for a better jitter and wander perfor-
mance of the device output clocks. The bandwidth for APLL1 and APLL2
is internally set to 22 kHz (typical).
The input of both APLLs can be derived from one of the DPLL1 out-
puts, as selected by the apll1_path_freq_cnfg[2:0] and apll2_path_fre-
q_cnfg[2:0] bits respectively as shown in Table 10. APLL2 is free-
running by default, after reset APLL2 should be set to be connected to
DPLL1 per Table 10.
Table 10: APLL1/2 input selection
apll1/apll2_path_freq_cnfg[2:0]
000
001
010
011-1111
APLL1/2 Input Selection
622.08 MHz from DPLL1
625 MHz from DPLL1
644.53125 MHz from DPLL1
Reserved
To following steps should be followed to set APLL1/APLL2 output to
Ethernet LAN PHY frequencies.
To initialize the device, write into the following registers:
1. Write 0x04F4F0 to bits apll1/apll2_divn_frac_cnfg[20:0] of
APLL1/APLL2 fractional feedback divider configuration register
to set the fractional part of feedback divider for APLL1/APLL2
2. Write 0x0051 to bits apll1/apll2_divn_den_cnfg[15:0] of APLL1/
APLL2 divisor denominator configuration register to set the
denominator part of feedback divider for APLL1/APLL2
3. Write 0x0010 to bits apll1/apll2_divisor_num_cnfg[15:0] of
APLL1/APLL2 divisor numerator configuration register to set the
numerator part of feedback divider for APLL1/APLL2
4. Write 0x21 to bits apll1/apll2_divisor_int_cnfg[5:0] of APLL1/
APLL2 divisor integer configuration register to set the integer part
of feedback divider for APLL1/APLL2
5. Write 0x13356218 to bits apll1/apll2_fr_ratio_cnfg[28:0] of
APLL1/APLL2 feedback divider configuration register to set the
feedback divider for APLL1/APLL2
After the device has been initialized according to the steps above,
follow the following steps when setting APLL1/APLL2 path to 644.53125
MHz:
• Write 1’b1 to dsm_cnfg_en bit to enable the preset programma-
ble feedback divider of APLL1/APLL2 configuration register
• Write the corresponding value in the apll1/apll2_path_fre-
q_cnfg[2:0] bits according to Table 10.
After the device has been initialized according to the steps 1 to 5
above, follow the following steps when setting APLL1/APLL2 path to
625MHz: or 622.08MHz
• Write 1’b0 to dsm_cnfg_en bit to disable the preset programma-
ble feedback divider of APLL1/APLL2 configuration register
• Write the corresponding value in the apll1/apll2_path_fre-
q_cnfg[2:0] bits according to Table 10.
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Revision 5, December 8, 2016