82P33731_16 Datasheet, PDF (33/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
If the frame sync input signal with respect to the DPLL1 selected
input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an
external sync alarm will be raised and the frame/sync input signal is dis-
abled to synchronize the frame/sync output signals. The external sync
alarm is cleared once the frame/sync input signal with respect to the
DPLL selected input clock is within the limit. If it is within the limit,
whether frame/sync input signal is enabled to synchronize the frame
sync output signal is determined by the AUTO_EXT_SYNC_EN bit and
the EXT_SYNC_EN bit.
When the frame/sync input signal is enabled to synchronize the
frame/sync output signal, it is adjusted to align itself with the DPLL
selected input clock.
By default, the falling edge of the frame/sync input signal is aligned
with the rising edge of the DPLL1 selected input clock. The rising edge
of frame/sync input signal can be set to be aligned with the rising edge
of the DPLL1 selected input clock by setting sync_edge bit to “1” in
DPLL1_sync_edge_cnfg register.
The EX_SYNC_ALARM_MON bit indicates whether frame/sync
input signal is in external sync alarm status. The external sync alarm is
indicated by the EX_SYNC_ALARM bit. If the EX_SYNC_ALARM bit is
‘1’, the occurrence of the external sync alarm will trigger an interrupt.
The 8 kHz frame pulse, the 2 kHz frame pulse, and the 1PPS sync
signal can be inverted by setting the 8K_1PPS_INV and 2K_1PPS_INV
bits of Frame Sync and Multiframe Sync Output Configuration Register.
The 8 kHz and the 2 kHz frame sync outputs can be 50:50 duty cycle
or pulsed, as determined by the 8K_PUL and 2K_PUL bits respectively.
When they are pulsed, the pulse width derived from DPLL1 is defined by
the period of OUT1. They are pulsed on the position of the falling or ris-
ing edge of the standard 50:50 duty cycle, as selected by the
2K_8K_PUL_POSITION bit of Frame Sync and Multiframe Sync Output
Configuration Register.
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Revision 5, December 8, 2016