82P33731_16 Datasheet, PDF (51/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
8.3.5
OUTPUT CLOCK DUTY CYCLE
Table 29: Output Clock Duty Cycle (OUT1 - OUT10)
Clock Output Frequency
Min
Typ
Max
Unit
Test Condition
f_OUT<570MHz
45
f_OUT>570MHz
35
NOTE: Output Duty Cycle configured using APLL1 or APLL2.
55
%
65
%
Table 30: Output Clock Duty Cycle (OUT11 to OUT12)
Clock Output Frequency
Min
Typ
Max
Unit
Test Condition
f_OUT<600MHz
47
f_OUT>600MHz
45
53
%
55
%
©2016 Integrated Device Technology, Inc.
51
Revision 5, December 8, 2016