82P33731_16 Datasheet, PDF (22/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
For the two conditions, the phase transients on the DPLL1 output are
minimized to be no more than 0.61 ns with HS. The HS can also be fro-
zen at the current phase offset by setting the hitless_switch_freeze bit in
DPLL1_mon_sw_pbo_cnfg register. When the HS is frozen, the device
will ignore any further HS events triggered by the above two conditions,
and maintain the current phase offset.
When the HS is disabled, there may be a phase shift on the DPLL1
output, as the DPLL1 output tracks back to 0 degree phase offset with
respect to the DPLL1 selected input clock. This phase shift can be lim-
ited; see section 3.2.2.1.9 Phase Slope Limit on page 22.
3.2.2.1.9 Phase Slope Limit
To meet the phase slope requirements of Telcordia and new ITU-T
standards, both DPLL1 provide a phase slope limiting feature to limit the
rate of output phase movement. The limit level is selectable via
DPLL1_ph_limit[2:0] bits in DPLL1_bw_overshoot_cnfg register. The
options are shown in Table 6.
Table 6: DPLL1 Phase Slope Limit
DPLL1_ph_limit[2:0]
Phase Slope Limit
000
61µs/s (GR-1244 ST3)
885ns/s (GR-1244-CORE ST2 and 3E,
001
GR-253-CORE ST3 and
G.8262 EEC option 2)
010
7.5 µs/s (G.813 opt1, G.8262 EEC-
option 1)
011
unlimited / 1.4 ms/s (default)
100
1 ns/s
101
5 ns/s
110
10 ns/s
111
programmable (default)*
*Note: The default phase slope limiting is set to programmable with a default
value set to 0 ns/s, therefore the phase slope limiting must be set to the proper
value to meet different standards according to this table.
The programmable phase slope limiting can be set by writing into
registers DPLL1_prog_ph_limit_cnfg[23:0]. The range of the program-
mable limit is 1484.3614 us/s.
3.2.2.1.10 Frequency Offset Limit
The DPLL1 output is limited to be within the programmed DPLL hard
limit (refer to Chapter 3.2.4.3).
3.2.2.2 DPLL2 Operating Mode
The DPLL2 operating mode is controlled by the DPLL2_OPERAT-
ING_MODE[2:0] bits, as shown in Table 7. DPLL2 is disabled by default,
write “0” to bit DPLL2_dpll_pdn in pdn_conf register to enable it.
Table 7: DPLL2 Operating Mode Control
DPLL2_OPERATING_MODE[2:0]
000
001
010
100
DPLL2 Operating Mode
Automatic
Forced - Free-Run
Forced - Holdover
Forced - Locked
When the operating mode is switched automatically, the operation of
the internal state machine is shown in Figure 8:
1
Free-Run mode
2
Locked mode
3
4
Holdover
mode
5
Figure 8. DPLL2 Automatic Operating Mode
Notes to Figure 8:
1. Reset.
2. An input clock is selected.
3. (The DPLL2 selected input clock is disqualified) OR (A qualified
input clock with a higher priority is switched to) OR (The DPLL2
selected input clock is switched to another one by Forced selec-
tion).
4. An input clock is selected.
5. No input clock is selected.
3.2.2.2.1 Free-Run Mode
In Free-Run mode, the DPLL2 output refers to the system clock and
is not affected by any input clock. The accuracy of the DPLL2 output is
equal to that of the system clock.
3.2.2.2.2 Locked Mode
In Locked mode, the DPLL2 is locked to the input clock. The phase
and frequency offset of the DPLL2 output track those of the DPLL2
selected input clock.
DPLL2 is a wide BW DPLL, with loop bandwidth higher than 25Hz.
3.2.2.2.3 Holdover Mode
In Holdover mode, the DPLL2 has 2 modes of operation for the hold-
over set by DPLL2_auto_avg bit in DPLL2_holdover_mode_cnfg regis-
ter.
DPLL2_auto_avg = 0: holdover frequency is the instantaneous value
of integral path just before entering holdover. If the DPLL2 was locked to
an input clock reference that has no in-band jitter/wander and was then
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Revision 5, December 8, 2016