82P33731_16 Datasheet, PDF (18/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
3.2.2.1.1 Free-Run Mode
In Free-Run mode, the DPLL1 output refers to the system clock and
is not affected by any input clock. The accuracy of the DPLL1 output is
equal to that of the system clock.
3.2.2.1.2 Pre-Locked Mode
In Pre-Locked mode, the DPLL1 output attempts to track the
selected input clock.
The Pre-Locked mode is a secondary, temporary mode.
3.2.2.1.3 Locked Mode
In Locked mode, the DPLL1 is locked to the input clock. The phase
and frequency offset of the DPLL1 output track those of the DPLL1
selected input clock.
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the DPLL1 attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the DPLL1_START_BW[4:0] bits and the
DPLL1_START_DAMPING[2:0] bits respectively.
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the DPLL1_ACQ_BW[4:0] bits and the
DPLL1_ACQ_DAMPING[2:0] bits respectively.
When the DPLL1 is locked, the locked bandwidth and damping factor
are used. They are set by the DPLL1_LOCKED_BW[4:0] bits and the
DPLL1_LOCKED_DAMPING[2:0] bits respectively.
The corresponding bandwidth and damping factor are used when the
DPLL1 operates in different locking stages: starting, acquisition and
locked, as controlled by the device automatically.
The locked bandwidth is selectable can be set as shown in Table 4.
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Revision 5, December 8, 2016