82P33731_16 Datasheet, PDF (41/68 Pages) IDEA.lnc. – Synchronous Ethernet

6
JTAG
This device is compliant with the IEEE 1149.1 Boundary Scan stan-
dard except the following:
• The output boundary scan cells do not capture data from the
core and the device does not support EXTEST instruction;
The JTAG interface timing diagram is shown in Figure - 18.
tTCK
TCK
tS
tH
TMS
TDI
tD
TDO
Figure 18. JTAG Interface Timing Diagram
Table 16: JTAG Timing Characteristics
Symbol
t_TCK
t_S
t_H
t_D
Parameter
TCK period
TMS / TDI to TCK setup time
TCK to TMS / TDI Hold Time
TCK to TDO delay time
Min
Typ
100
25
25
82P33731 Datasheet
Max
Unit
ns
ns
ns
50
ns
©2016 Integrated Device Technology, Inc.
41
Revision 5, December 8, 2016