82P33731_16 Datasheet, PDF (26/68 Pages) IDEA.lnc. – Synchronous Ethernet

82P33731 Datasheet
3.2.3.2.3 Frequency Monitoring
Frequency is monitored by comparing the input clock with a refer-
ence clock. The reference clock can be derived from the system clock or
the output of DPLL1, as determined by the FREQ_MON_CLK bit.
Each reference clock has a hard frequency monitor and a soft fre-
quency monitor. Both monitors have two thresholds, rejecting threshold
and accepting threshold, which are set in HARD_FREQ_MON_-
THRESHOLD[7:0] and SOFT_FREQ_MON_THRESHOLD[7:0]. So four
frequency alarm thresholds are set for frequency monitoring: Hard Alarm
Accepting Threshold, Hard Alarm Rejecting Threshold, Soft Alarm
Accepting Threshold and Soft Alarm Rejecting Threshold.
The frequency hard alarm accepting threshold can be calculated as
follows:
Frequency Hard Alarm Accepting Threshold (ppm) = (HARD_FRE-
Q_MON_THRESHOLD[7:4] + 1) X FREQ_MON_FACTOR[3:0] (b3~0,
FREQ_MON_FACTOR_CNFG)
The frequency hard alarm rejecting threshold can be calculated as
follows:
Frequency Hard Alarm Rejecting Threshold (ppm) = (HARD_FRE-
Q_MON_THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] (b3~0,
FREQ_MON_FACTOR_CNFG)
When the input clock frequency rises to above the hard alarm reject-
ing threshold, the INn_FREQ_HARD_ALARM bit (14  n  1) will alarm
and indicate ‘1’. The alarm will remain until the frequency is down to
below the hard alarm accepting threshold, then the INn_FRE-
Q_HARD_ALARM bit will return to ‘0’. There is a hysteresis between fre-
quency monitoring, refer to Figure 11. Hysteresis Frequency Monitoring
page 26.
The soft alarm is indicated by the INn_FREQ_SOFT_ALARM bit (14
 n  1) in the same way as hard alarm.
If the FREQ_MON_HARD_EN bit is ‘1’, the frequency alarm status of
the input clock is indicated by the INn_FREQ_HARD_ALARM bit (14  n
 1). When the FREQ_MON_HARD_EN bit is ‘0’, no frequency hard
alarm is raised even if the input clock is above the frequency alarm
threshold.
The input clock with a frequency hard alarm is disqualified for clock
selection for the DPLLs, but the soft alarm doesn’t affect the clock selec-
tion for the DPLLs.
The frequency of each input clock with respect to the reference clock
can be read by doing the following step:
1. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate
as follows:
Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] * FRE-
Q_MON_FACTOR[3:0]
Note that the value set by the FREQ_MON_FACTOR[3:0] bits
depends on the application.
Rejecting threshold
Accepting threshold
accepted
rejected (alarmed)
Figure 11. Hysteresis Frequency Monitoring
accepted
©2016 Integrated Device Technology, Inc.
26
Revision 5, December 8, 2016