ICSSSTUB32871A Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – 27-Bit Registered Buffer for DDR2

ICSSSTUB32871A
Register Timing
RESET
DCSn
CK ⁽¹⁾
CK ⁽¹⁾
Dn ⁽¹⁾
Qn
PARIN ⁽¹⁾
PTYERR
tINACT
tRPHL
RESET to Q
tRPLH
RESET to PTYERR
H, L, or X
H or L
Figure 6 — RESET switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic
levels (not floating) for a minimum time of t _INACT (max)
1186G—04/16/07
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